FRAME PROCESSING CIRCUIT
A frame processing circuit performs frame processing that is creation processing of creating an RFID data frame from a payload or analysis processing of analyzing an RFID data frame and obtaining a payload. The frame processing includes m (1≦m≦n) number of processing steps according to a type of data frame among n (n is an integer of 2 or above) number of processing steps. The frame processing circuit includes n-number of processing blocks that respectively execute the n-number of processing steps. The n-number of processing blocks include a bypassable block where setting of whether to bypass processing can be made according to a type of data frame, that performs processing of a relevant step on received data and outputs processed data if no bypassing is set, and outputs received data without performing any processing if bypassing is set.
1 . A frame processing circuit for performing frame processing that is creation processing of creating an RFID data frame from a payload or analysis processing of analyzing an RFID data frame and obtaining a payload, the frame processing including m (1≦m≦n) number of processing steps according to a type of data frame among n (n is an integer of 2 or above) number of processing steps, the circuit comprising:
n-number of processing blocks that respectively execute the n-number of processing steps,
wherein the n-number of processing blocks include a bypassable block where setting of whether to bypass processing can be made according to a type of data frame, that performs processing of a relevant step on received data and outputs processed data if no bypassing is set, and outputs received data without performing any processing if bypassing is set.
2 . The frame processing circuit according to claim 1 , wherein the type of data frame involves a type of data format in one protocol.
3 . The frame processing circuit according to claim 1 , wherein the type of data frame involves a type of protocol.
4 . The frame processing circuit according to claim 2 , wherein the type of data frame involves a type of protocol.
5 . The frame processing circuit according to claim 1 , wherein the n-number of processing blocks include a parameter variable block where setting of a parameter to be used for processing of a relevant step can be made according to a type of data frame, that performs processing of the step by referring to the set parameter.
6 . The frame processing circuit according to claim 1 , wherein the bypassable block comprises:
a main processing unit that executes processing of a relevant step on received data;
a bypass that outputs received data without performing any processing;
a pass setting register where a set value indicating whether to bypass processing is writable; and
a pass switch that switches between outputting data from a previous stage to the main processing unit and outputting the data to the bypass based on the set value written to the pass setting register.
7 . The frame processing circuit according to claim 2 , wherein the bypassable block comprises:
a main processing unit that executes processing of a relevant step on received data;
a bypass that outputs received data without performing any processing;
a pass setting register where a set value indicating whether to bypass processing is writable; and
a pass switch that switches between outputting data from a previous stage to the main processing unit and outputting the data to the bypass based on the set value written to the pass setting register.
8 . The frame processing circuit according to claim 3 , wherein the bypassable block comprises:
a main processing unit that executes processing of a relevant step on received data;
a bypass that outputs received data without performing any processing;
a pass setting register where a set value indicating whether to bypass processing is writable; and
a pass switch that switches between outputting data from a previous stage to the main processing unit and outputting the data to the bypass based on the set value written to the pass setting register.
9 . The frame processing circuit according to claim 4 , wherein the bypassable block comprises:
a main processing unit that executes processing of a relevant step on received data;
a bypass that outputs received data without performing any processing;
a pass setting register where a set value indicating whether to bypass processing is writable; and
a pass switch that switches between outputting data from a previous stage to the main processing unit and outputting the data to the bypass based on the set value written to the pass setting register.
10 . The frame processing circuit according to claim 5 , wherein the bypassable block comprises:
a main processing unit that executes processing of a relevant step on received data;
a bypass that outputs received data without performing any processing;
a pass setting register where a set value indicating whether to bypass processing is writable; and
a pass switch that switches between outputting data from a previous stage to the main processing unit and outputting the data to the bypass based on the set value written to the pass setting register.
11 . The frame processing circuit according to claim 5 , wherein
the parameter variable block comprises:
a main processing unit that executes processing of a relevant step on received data; and
a parameter register where the parameter is writable, and
the main processing unit executes processing of the step by using the parameter written to the parameter register.
12 . The frame processing circuit according to claim 10 , wherein
the parameter variable block comprises:
a main processing unit that executes processing of a relevant step on received data; and
a parameter register where the parameter is writable, and
the main processing unit executes processing of the step by using the parameter written to the parameter register.
13 . The frame processing circuit according to claim 1 , wherein the n-number of processing blocks include a processing scheme variable block comprising a plurality of main processing units that execute processing of a relevant step by different schemes and capable of switching among the plurality of main processing units according to a type of data frame.
14 . The frame processing circuit according to claim 13 , wherein the processing scheme variable block comprises:
a processing scheme setting register where a set value indicating a processing scheme of a relevant step is writable; and
a scheme switch that switches among the plurality of main processing units based on the set value written to the processing scheme setting register.
15 . The frame processing circuit according to claim 1 , wherein
the frame processing circuit performs the creation processing, and
the n-number of processing blocks respectively execute CRC processing, parity processing, encoding, start data processing and end data processing.
16 . The frame processing circuit according to claim 1 , wherein
the frame processing circuit performs the analysis processing, and
the n-number of processing blocks respectively execute start data processing, end data processing, decoding, parity processing and CRC processing.
17 . A frame processing chip comprising:
a frame creation circuit that is the frame processing circuit according to claim 15 ; and
a frame analysis circuit that is a frame processing circuit for performing frame processing that is creation processing of creating an RFID data frame from a payload or analysis processing of analyzing an RFID data frame and obtaining a payload, the frame processing including m (1≦m≦n) number of processing steps according to a type of data frame among n (n is an integer of 2 or above) number of processing steps, the circuit comprising:
n-number of processing blocks that respectively execute the n-number of processing steps,
wherein the n-number of processing blocks include a bypassable block where setting of whether to bypass processing can be made according to a type of data frame, that performs processing of a relevant step on received data and outputs processed data if no bypassing is set, and outputs received data without performing any processing if bypassing is set; wherein
the frame processing circuit performs the analysis processing, and
the n-number of processing blocks respectively execute start data processing, end data processing, decoding, parity processing and CRC processing.
18 . An RFID reader/writer comprising:
an antenna;
an RF modulation/demodulation unit that performs RF modulation of a data frame from the frame processing chip according to claim 17 and outputs a result to the antenna, and performs RF demodulation of a signal received by the antenna and outputs a result to the frame processing chip; and
a data command processing unit including a CPU, that performs control processing including supply of a payload to the frame processing chip, processing of a payload from the frame processing chip, and setting of each processing block in the frame processing chip.