Semiconductor device and bias generation circuit

1. A semiconductor device having a first operation section operable at a first power supply voltage, a second operation section operable at a second power supply voltage differing from the first power supply voltage and a bias generation circuit, the bias generation circuit comprising:

a first power supply voltage input section that inputs the first power supply voltage;

a second power supply voltage input section that inputs the second power supply voltage;

a regulator circuit that generates a back bias voltage on the basis of the second power supply voltage, the back bias voltage being varied in accordance with a combination of bit values inputted to the regulator circuit;

a selector that selects either the first power supply voltage or the back bias voltage generated by the regulator circuit as an output voltage;

an output section that outputs the output voltage; and

a short circuit that short-circuits the back bias voltage to the first power supply voltage to equalize potentials of the back bias voltage and the first power supply voltage,

wherein the regulator circuit is turned off and the short circuit is turned on when power is applied to the semiconductor integrated circuit apparatus or when a source of the second power supply voltage is tuned off while the regulator circuit operates, and

when the second voltage source is turned on before the first voltage source is turned on in response to the semiconductor device being switched on, the second power supply voltage is turned off, the short circuit is turned on, and the regulator circuit is turned off in response to the semiconductor device being switched off while the first power supply voltage is maintained on, and thereafter the first power supply voltage is turned off.

2. The semiconductor device according to claim 1 , wherein the bias generation circuit further comprises a reference voltage generation circuit that generates a reference voltage to be a reference in generating the back bias voltage.

3. The semiconductor device according to claim 1 , wherein the selector selects the first power supply voltage as the output voltage in the bias generation circuit when power is applied to the semiconductor device.

4. The semiconductor device according to claim 1 , wherein the regulator circuit comprises a PMOS driver.

5. A bias generation circuit provided in a semiconductor device and generating a back bias voltage to be applied to a transistor in the semiconductor device, the bias generation circuit comprising:

a first power supply voltage input section that inputs a first power supply voltage;

a second power supply voltage input section that inputs a second power supply voltage differing from the first power supply voltage;

a regulator circuit that generates the back bias voltage on the basis of the second power supply voltage, the back bias voltage being varied in accordance with a combination of bit values inputted to the regulator circuit; a selector that selects either the first power supply voltage or the back bias voltage generated by the regulator circuit as an output voltage;

an output section that outputs the output voltage; and

a short circuit that short-circuits the back bias voltage to the first power supply voltage to equalize potentials of the back bias voltage and the first power supply voltage,

wherein the regulator circuit is turned off and the short circuit is turned on when power is applied to the semiconductor integrated circuit apparatus or when a source of the second power supply voltage is tuned off while the regulator circuit operates, and

wherein, when the second voltage source is turned on before the first voltage source is turned on in response to the semiconductor device being switched on, the second power supply voltage is turned off, the short circuit is turned on, and the regulator circuit is turned off while the first power supply voltage is maintained on in response to the semiconductor device being switched off, and thereafter the first power supply voltage is turned off.

6. The bias generation circuit according to claim 5 further comprising a reference voltage generation circuit that generates a reference voltage to be a reference in generating the back bias voltage.

7. The bias generation circuit according to claim 5 , wherein the selector selects the first power supply voltage as the output voltage when power is applied to the semiconductor device.

8. The bias generation circuit according to claim 5 , wherein the regulator circuit comprises a PMOS driver.

9. The semiconductor device according to claim 1 , wherein the regulator circuit comprises a variable resistor.

10. The semiconductor device according to claim 9 , wherein the regulator circuit varies the generated back vias voltage by changing a resistance of the variable resistor in accordance with the combination of bit values.

11. The semiconductor device according to claim 1 , wherein the back bias voltage is switched to the first power supply voltage when a source of the second power supply voltage is disabled while the regulator circuit operates.

12. The bias generation circuit according to claim 5 , wherein the regulator circuit comprises a variable resistor.

13. The bias generation circuit according to claim 12 , wherein the regulator circuit varies the generated back vias voltage by changing a resistance of the variable resistor in accordance with the combination of bit values.

14. The bias generation circuit according to claim 5 , wherein the back bias voltage is switched to the first power supply voltage when a source of the second power supply voltage is disabled while the regulator circuit operates.