Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

1. A behavioral synthesis apparatus comprising:

a acquisition unit configured to acquire a behavioral level description describing an operation of a semiconductor integrated circuit;

a scheduling unit configured to separate the acquired behavioral level description into N stage descriptions, and schedule input/output operations and computations among the N stage descriptions; and

a generation unit configured to generate a register transfer level description describing a configuration, layout and interconnection of the semiconductor integrated circuit based on the N stage descriptions and a result of scheduling performed by the scheduling unit to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit, the generation unit generating the register transfer level description,

wherein for each integer i=1, 2, . . . , N−1, an output of an ith stage circuit becomes an input to an (i+1)th stage circuit, and

wherein the state control circuit updates the stage control states of the semiconductor integrated circuit in order from a first stage control state to an (N−1)th stage control state, then repeats an Nth stage control state a predetermined number of times, then updates the stage control states of the semiconductor integrated circuit in order from an (N+1)th stage control state to an (2N−1)th stage control state, and

wherein when a current stage control state is a jth stage control state, the state control circuit:

(a) operates the first to jth stage circuits and stops (j+1)th to Nth stage circuits when j is an integer equal to or greater than 1 and less than N,

(b) operates the first to Nth stage circuits when j is equal to N, and

(c) stops the first to (j−N)th stage circuits and operates (j−N+1)th to Nth stage circuits when j is greater than N.

2. The behavioral synthesis apparatus according to claim 1 , wherein the generation unit is configured to generate the register transfer level description,

wherein

each of the 2N−1 stage control states is separated into M operational states, and

wherein when a current operational state is a kth operational state, the state control circuit changes the configuration, layout and interconnection of the semiconductor integrated circuit to a kth context.

3. A behavioral synthesis apparatus comprising:

acquisition means configured to acquire a behavioral level description describing an operation of a semiconductor integrated circuit;

scheduling means configured to separate the acquired behavioral level description into N stage descriptions, and schedule input/output operations and computations among the N stage descriptions; and

generation means configured to generate a register transfer level description describing a configuration, layout and interconnection of the semiconductor integrated circuit based on the N stage descriptions and a result of scheduling performed by the scheduling means to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit,

the generation means generating the register transfer level description,

wherein for each integer i=1, 2, . . . , N−1, an output of an ith stage circuit becomes an input to an (i+1)th stage circuit, and

wherein the state control circuit updates the stage control states of the semiconductor integrated circuit in order from a first stage control state to an (N−1)th stage control state, then repeats an Nth stage control state a predetermined number of times, then updates the stage control states of the semiconductor integrated circuit in order from an (N+1)th stage control state to an (2N−1)th stage control state, and

wherein when a current stage control state is a jth stage control state, the state control circuit:

(a) operates the first to jth stage circuits and stops (j+1)th to Nth stage circuits when j is an integer equal to or greater than 1 and less than N,

(b) operates the first to Nth stage circuits when j is equal to N, and

(c) stops the first to (j−N)th stage circuits and operates (j−N+1)th to Nth stage circuits when j is greater than N.

4. The behavioral synthesis apparatus according to claim 3 , wherein the generation means is configured to generate the register transfer level description,

wherein each of the 2N−1 stage control states is separated into M operational states, and

wherein when a current operational state is a kth operational state, the state control circuit changes the configuration, layout and interconnection of the semiconductor integrated circuit to a kth context.

5. A behavioral synthesis method to be executed by a behavioral synthesis apparatus including an acquisition unit, a scheduling unit and a generation unit, comprising:

an acquisition step of causing the acquisition unit to acquire a behavioral level description describing an operation of a semiconductor integrated circuit;

a scheduling step of causing the scheduling unit to separate the acquired behavioral level description into N stage descriptions, and schedule input/output operations and computations among the N stage descriptions; and

a generation step of causing the generation unit to generate a register transfer level description describing a configuration, layout and interconnection of the semiconductor integrated circuit based on the N stage descriptions and a result of scheduling performed by the scheduling unit to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit,

the generation unit generating the register transfer level description,

wherein for each integer i=1, 2, . . . , N−1, an output of an ith stage circuit becomes an input to an (i+1)th stage circuit, and

wherein the state control circuit updates the stage control states of the semiconductor integrated circuit in order from a first stage control state to an (N−1)th stage control state, then repeats an Nth stage control state a predetermined number of times, then updates the stage control state of the semiconductor integrated circuit in order from an (N+1)th stage control state to an (2N−1)th stage control state, and

when a current stage control state is a jth stage control state, the state control circuit:

(a) operates the first to jth stage circuits and stops (j+1)th to Nth stage circuits when j is an integer equal to or greater than 1 and less than N,

(b) operates the first to Nth stage circuits when j is equal to N, and

(c) stops the first to (j−N)th stage circuits and operates (j−N+1)th to Nth stage circuits when j is greater than N.

6. The behavioral synthesis method according to claim 5 , wherein the generation unit generates the register transfer level description,

wherein each of the 2N−1 stage control states is separated into M operational states, and

wherein when a current operational state is a kth operational state, the state control circuit changes the configuration, layout and interconnection of the semiconductor integrated circuit to a kth context.

7. A computer readable recording device recording a program allowing a computer to function as:

an acquisition unit configured to acquire a behavioral level description describing an operation of a semiconductor integrated circuit;

a scheduling unit configured to separate the acquired behavioral level description into N stage descriptions, and schedule input/output operations and computations among the N stage descriptions; and

a generation unit configured to generate a register transfer level description describing a configuration, layout and interconnection of the semiconductor integrated circuit based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit,

the generation unit generating the register transfer level description,

wherein for each integer i=1, 2, . . . , N−1, an output of an ith stage circuit becomes an input to an (i+1)th stage circuit, and

wherein the state control circuit updates the stage control states of the semiconductor integrated circuit in order from a first stage control state to an (N−1)th stage control state, then repeats an Nth stage control states a predetermined number of times, then updates the stage control states of the semiconductor integrated circuit in order from an (N+1)th stage control state to an (2N−1)th stage control state, and

wherein when a current stage control state is a jth stage control state, the state control circuit:

(a) operates the first to jth stage circuits and stops (j+1)th to Nth stage circuits when j is an integer equal to or greater than 1 and less than N,

(b) operates the first to Nth stage circuits when j is equal to N, and

(c) stops the first to (j−N)th stage circuits and operates (j−N+1)th to Nth stage circuits when j is greater than N.