A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3 , a capacitor element 4 and a connection wiring 6 . The connection wiring 6 includes a first polysilicon layer 13 a above a substrate 10 , and a first silicide layer 14 a which connects the resistance element 3 and the capacitor element 4 and is on the first polysilicon layer 13 a . The capacitor element 4 includes a diffusion layer 12 b in the surface region of the semiconductor substrate 10 , a gate insulating layer 15 b on the diffusion layer 12 b , a second polysilicon layer 13 b on the gate insulating layer 15 b , and a second silicide layer 14 b on the second polysilicon layer 13 b . The resistance element 3 includes a third polysilicon layer 13 c above the semiconductor substrate 10 . The first, second and third polysilicon layers 13 a, 13 b and 13 c are integrally provided. The first and second silicide layers 14 a and 14 b are integrally provided.
1. A delay circuit, comprising:
a resistance element;
a capacitor element; and
a connection wiring including a first silicide layer connecting said resistance element and said capacitor element,
wherein said connection wiring further includes
a first polysilicon layer provided above a semiconductor substrate,
said first silicide layer being provided on said first polysilicon layer,
said capacitor element includes:
a diffusion layer provided in a surface region of said semiconductor substrate,
a gate insulating layer provided on said diffusion layer,
a second polysilicon layer provided on said gate insulating layer, and
a second silicide layer provided on said second polysilicon layer, said resistance element includes
a third polysilicon layer provided above said semiconductor substrate,
said first polysilicide layer, said second polysilicide layer, and said third polysilicon layer are integrally provided, and
said first silicide layer and said second silicide layer are integrally provided.
2. The delay circuit according to claim 1 ,
wherein said resistance element, said capacitor element and said connection wiring are regions without upper layer metal restriction.
3. The delay circuit according to claim 1 , further comprising:
a first inverter circuit provided at an input side;
a first wiring which connects said first inverter circuit and said resistance element;
a second inverter circuit provided at an output side; and
a second wiring which connects said second inverter circuit and said capacitor element,
wherein said first wiring includes a fourth silicide layer which connects to said resistance element, and
said second wiring includes a fifth silicide layer which connects to said capacitor element.
4. The delay circuit according to claim 3 ,
wherein said first wiring further includes
a fourth polysilicon layer provided integrally with said third polysilicon layer,
said fourth silicide layer being provided on said fourth polysilicon layer,
said second wiring further includes
a fifth polysilicon layer provided integrally with said second polysilicon layer,
said fifth silicide layer being provided on said fifth polysilicon layer integrally with said second silicide layer, and
said fourth silicide layer is provided in the same layer as said fifth silicide layer.
5. The delay circuit according to claim 1 ,
wherein said resistance element includes
a seventh silicide layer provided to cover part of said third polysilicon layer, and
said seventh silicide layer is provided in the same layer as said first silicide layer, and a resistance value of said resistance element is set based on an area covering said third polysilicon layer.
6. The delay circuit according to claim 1 ,
wherein said resistance element is in a rectangular shape.
7. The delay circuit according to claim 6 ,
wherein said resistance element includes
a plurality of rectangular parts, and
an internal wiring including a sixth silicide layer connecting respective said plurality of rectangular parts in series to one another, and
said sixth silicide layer is provided in the same layer as said first silicide layer.