Power semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.
1. A method of manufacturing a semiconductor device, comprising:
preparing a semiconductor substrate having a high-voltage device region and a low-voltage device region;
forming a field insulating layer in the high-voltage device region;
forming a first gate oxide layer on exposed surfaces of the semiconductor substrate;
etching part of the field insulating layer to form a stepped field insulating layer and etching part of the first gate oxide layer to expose the semiconductor substrate in the low-voltage device region;
forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region; and
forming a gate poly over part of the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.
2. The method according to claim 1 , wherein the gate poly has a stepped structure with a same profile as the stepped field insulating layer.
3. The method according to claim 1 , further comprising:
forming a second conductivity-type epitaxial layer as part of the semiconductor substrate;
forming an embedded insulation layer in the second conductivity-type epitaxial layer in the high-voltage device region;
forming a high-voltage first conductivity-type well region and a second conductivity-type body region in the semiconductor substrate above the embedded insulation layer, by implanting impurities in the high-voltage device region;
forming a source region doped with first conductivity-type impurities and a second conductivity-type source contact region adjoining the source region, by implanting impurities in part of the second conductivity-type body region; and
forming a first conductivity-type low-voltage well and a first conductivity-type drain region, by implanting impurities in the high-voltage first conductivity-type well region.
4. The method according to claim 1 , wherein etching part of the field insulating layer and etching part of the first gate oxide layer are performed simultaneously.
5. The method according to claim 4 , further comprising continuing to etch the part of the field insulating layer after the part of the first gate oxide layer is completely etched.
6. A method of manufacturing a semiconductor device, comprising:
forming a field insulating layer in a high-voltage device region of a semiconductor substrate;
forming a first gate oxide layer on exposed surfaces of the semiconductor substrate;
simultaneously etching part of the field insulating layer and the first gate oxide layer in the low-voltage device region to expose the semiconductor substrate in the low-voltage device region and form a stepped field insulating layer;
forming a second gate oxide layer with the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region; and
forming a gate over part of the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.
7. The method according to claim 6 , wherein the semiconductor substrate comprises a second conductivity-type epitaxial layer.
8. The method according to claim 7 , further comprising forming an embedded insulation layer in the epitaxial layer in the high-voltage device region.
9. The method according to claim 8 , further comprising implanting first conductivity-type impurities above the embedded insulation layer to form a high-voltage well region.
10. The method according to claim 8 , further comprising implanting second conductivity-type impurities above the embedded insulation layer to form a body region.
11. The method according to claim 10 , further comprising implanting first conductivity-type impurities in the body region to form a source region.
12. The method according to claim 11 , further comprising implanting second conductivity-type impurities in the body region adjoining the source region to form a source contact region.
13. The method according to claim 10 , further comprising implanting first conductivity-type impurities in a part of the high-voltage well region opposite to the field insulating layer to form a low-voltage well.
14. The method according to claim 11 , further comprising implanting first conductivity-type impurities in a part of the high-voltage well region opposite to the field insulating layer to form a drain region.
15. The method according to claim 14 , wherein the source region and the drain region are formed simultaneously.
16. The method according to claim 6 , further comprising forming one or more additional gates over the second gate oxide layer in the low-voltage device region.
17. The method according to claim 6 , further comprising continuing to etch the part of the field insulating layer after the part of the first gate oxide layer is completely etched.