Semiconductor device with trench of various widths
View Patent ↗A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.
1. A semiconductor device, comprising:
a substrate, disposed with a dielectric layer thereon, wherein a trench is disposed in the dielectric layer;
a gate structure, located in the trench and comprising a high dielectric constant layer, a work function metal layer, and a metal layer sequentially disposed on the substrate; and
a source/drain region, disposed in the substrate at respective sides of the gate structure,
wherein the trench comprises a top, a bottom, and a neck arranged between the top and the bottom, a width of the neck is narrower than a width of the top, and the width of the neck is narrower than or equal to a width of the bottom.
2. The semiconductor device as claimed in claim 1 , wherein the top and the neck have a first height therebetween, the neck and the bottom have a second height therebetween, and a ratio of the first height to the second height is substantially 2:1.
3. The semiconductor device as claimed in claim 1 , wherein an included angle between a sidewall of the top of each of the plurality of trenches and a surface of the dielectric layer is larger than 90°.
4. The semiconductor device as claimed in claim 1 , further comprising an insulation layer disposed between the substrate and the high dielectric constant layer.
5. The semiconductor device as claimed in claim 1 , wherein the source/drain region is a doped region or an epitaxial layer.
6. The semiconductor device as claimed in claim 1 , further comprising a spacer disposed on a sidewall of the gate structure.