Packet relay device
The packet relay device includes a clock generation portion adapted to generate a clock signal of prescribed frequency as a standard for operation of the packet relay device; a timer portion adapted to count up a timer value over a first number of clock cycles on the basis of the clock signal; a relay control portion adapted relay received packets while limiting to a prescribed amount of packets the amount of packets forwardable per a predetermined increment of the timer value; and a power control portion adapted to reduce the frequency of the clock signal to 1/n in order to reduce power consumption by the packet relay device. If the frequency of the clock signal has been reduced to 1/n by the power control portion, the timer portion counts up the timer value over a number of clock cycles equivalent to 1/n the aforementioned number of clock cycles.
1. A packet relay device for relaying packets flowing through a network, comprising:
a receiving portion that receives packets from the network;
a clock generation portion that generates a clock signal of a prescribed frequency as a standard for operation of the packet relay device;
a timer portion that counts up a timer value over a first number of clock cycles based on the clock signal;
a relay control portion that receives the timer value from the timer portion, and relays the received packets to a destination specified by header information of the packets while limiting the amount of packets forwardable per a predetermined increment of the timer value to a prescribed amount of packets;
a power control portion that controls the clock generation portion to reduce the frequency of the clock signal to 1/N, so as to reduce power consumption by the packet relay device, where N is a real number greater than 1;
wherein:
when switching a power mode from a normal mode to a power saving mode based on amount of packets received by the receiving portion, the power control portion generates an instruction for both the timer portion and the clock generation portion;
the clock generation portion reduces the frequency of the clock signal to 1/N in response to the instruction from the power control portion; and
the timer portion includes:
a normal timer portion that counts up a first timer value over the first number of clock cycles;
a power saving timer portion that counts up a second timer value over the second number of clock cycles equivalent to 1/N of the first number of clock cycles; and
a selector circuit that selects, according to the instruction from the power control portion, either the first timer value counted up by the normal timer portion or the second timer value counted up by the power saving timer portion, as the timer value that is output to the relay control portion.
2. The packet relay device according to claim 1 , wherein the relay control portion determines that the received packets cause bandwidth violation, when the amount of the received packets per the predetermined increment of the timer value that is counted up by either the normal timer portion or the power saving timer portion which is selected by the selector circuit.
3. The packet relay device according to claim 2 , wherein the relay control portion detects flows of the received packets based on the header information, and performs the limiting the amount of the packets separately for each of the flows.
4. The packet relay device according to claim 3 , wherein
the timer portion is capable of outputting both a first timer value that is counted up over the first number of clock cycles and a second timer value that is counted up over the second number of clock cycles, even if the frequency of the clock signal has been reduced to 1/N by the power control portion; and
separately for each of the flows, the relay control portion selects, based on a prescribed setting, whether to use the first timer value or the second timer value.
5. The packet relay device according to claim 1 , wherein
the relay control portion performs the limiting the amount of the packets by delaying transmission timings of the received packets, depending on packet length of the received packets and the amount of packets forwardable per the predetermined increment of the timer value that is counted up by either the normal timer portion or the power saving timer portion which is selected by the selector circuit.
6. The packet relay device according to claim 5 , wherein
the relay control portion queues the received packets separately for the each destination, and performs the limiting the amount of the packets separately for the each destination.
7. The packet relay device according to claim 6 , wherein
the timer portion is capable of outputting both a first timer value that is counted up over the first number of clock cycles and a second timer value that is counted up over the second number of clock cycles, even if the frequency of the clock signal has been reduced to 1/N by the power control portion; and
separately for the each destination, the relay control portion selects, based on a prescribed setting, whether to use the first timer value or the second timer value.