Semiconductor device
View Patent ↗A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.
1. A semiconductor device comprising:
an even number of transistor pairs, each transistor pair being a transistor pair in which an n-type transistor and a p-type transistor are connected in series between a power supply terminal and a ground terminal, the even number being a four or more;
connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and
inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the n-type transistor of one of the transistor pairs disposed in the preceding stage of one of the transistor pairs for which each connection node is provided and a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein
the even number of transistor pairs constitute a state storage circuit in such a manner that the transistor pairs are connected in the form of a loop, and
any one of the transistor pairs is referred to as a first transistor pair, the n-type transistor of the first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.
2. The semiconductor device according to claim 1 , wherein the p-well region in which the n-type transistor of the first transistor pair is disposed is one of a plurality of p-well regions defined by at least one n-well region, the n-well region being an n-well region in which the p-type transistors are disposed.
3. The semiconductor device according to claim 1 , wherein
the semiconductor device comprises the four transistor pairs, and
the four n-type transistors of the transistor pairs are disposed in two p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed.
4. The semiconductor device according to claim 3 , wherein
the p-well region in which the n-type transistor of the first transistor pair is disposed is one of two p-well regions defined by one n-well region, and
the four p-type transistors of the transistor pairs are disposed in the n-well region.
5. The semiconductor device according to claim 1 , wherein
the semiconductor device comprises the six transistor pairs, and
the six n-type transistors of the transistor pairs are disposed in three p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed.
6. The semiconductor device according to claim 5 , wherein
three p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed are defined by two n-well regions, and
the six p-type transistors of the transistor pairs are arbitrarily disposed in the two n-well regions.
7. The semiconductor device according to claim 1 , wherein
the semiconductor device comprises the eight transistor pairs, and
the eight n-type transistors of the transistor pairs are disposed in two p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed.
8. The semiconductor device according to claim 7 , wherein
two p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed are defined by one n-well region, and
the eight p-type transistors of the transistor pairs are disposed in the n-well region.
9. The semiconductor device according to claim 1 , wherein
p-well regions including the p-well region in which the n-type transistor of the first transistor pair is disposed and an n-well region are fixed regions whose disposition is previously determined, and
the semiconductor device is configured as a standard cell where the n-type transistors and the p-type transistors constituting the state storage circuit are disposed in the fixed regions.