Accessing a phase change memory
View Patent ↗A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying a current to the phase change memory cell that is sufficient for the intended access operation and greater than that provided directly by the current source.
1. An apparatus, comprising:
a phase-change memory cell;
a first current source, said first current source comprising a first capacitor, said first capacitor discharging to provide a first current to said phase-change memory cell during a memory access; and
a second current source, said second current source providing a second current to said phase-change memory during said memory access.
2. The apparatus of claim 1 , wherein said first current is insufficient to accomplish said memory access.
3. The apparatus of claim 2 , wherein the combination of said first current and said second current is sufficient to accomplish said memory access.
4. The apparatus of claim 1 , wherein said first capacitor comprises a conductive line, said conductive line in electrical communication with said phase-change memory cell.
5. The apparatus of claim 1 , wherein said first capacitor comprises a MOS capacitor.
6. The apparatus of claim 1 , wherein said second current source comprises a second capacitor, said second capacitor discharging to provide said second current.
7. The apparatus of claim 6 , wherein the capacitance of said first capacitor and the capacitance of said second capacitor are additive.
8. An apparatus, comprising:
a phase-change memory cell;
a first current source, said first current source providing a first current to said phase-change memory cell during a memory access; said memory access being a set operation or a reset operation; and
a second current source, said second current source providing a second current to said phase-change memory during said memory access.
9. The apparatus of claim 1 , wherein said first current and said second current are provided simultaneously.
10. An apparatus, comprising:
a phase-change memory cell;
a first current source, said first current source providing a first current to said phase-change memory cell during a memory access;
a second current source, said second current source providing a second current to said phase-change memory during said memory access; and
a third current source, said third current source providing a third current to said phase-change memory cell during said memory access.
11. A method of operating a phase-change memory cell, comprising:
providing a phase-change memory cell;
initiating a memory access of said phase-change memory cell;
charging a first capacitor;
discharging said first capacitor to provide a first current during said memory access;
providing a second current during said memory access; and
terminating said memory access.
12. The apparatus of claim 11 , wherein said first current is insufficient to accomplish said memory access.
13. The apparatus of claim 12 , wherein the combination of said first current and said second current is sufficient to accomplish said memory access.
14. The method of claim 11 , wherein said charging of said first capacitor occurs before said initiating said memory access.
15. The method of claim 11 , wherein the time of said charging of said first capacitor is greater than the time of said memory access.
16. The method of claim 11 , wherein said second current charges said first capacitor.
17. The method of claim 11 , further comprising:
charging a second capacitor; and
discharging said second capacitor to provide said second current.
18. The apparatus of claim 8 , wherein the current capacity of said first current source is insufficient to accomplish said memory access.