Parallel bitline nonvolatile memory employing channel-based processing technology
View Patent ↗Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.
1. A non-volatile memory device, comprising:
a parallel bitline semiconductor architecture comprising a plurality of wordlines, and a plurality of transistors, each of the plurality of transistors having a gate that is electrically connected to respective ones of the plurality of wordlines a source node that is electrically connected directly to a local source line and a drain node that is electrically connected directly to a local bitline, wherein the local source line is connected to a common source line via a select transistor and the local bitline is connected to a common bit line by a second select transistor; and
a channel-based processing component configured to ground the local source line and the local bitline to program one transistor of the plurality of transistors, wherein the channel-based processing component inhibits programming of a non-program transistor sharing a common wordline with the one transistor by floating a second local source line and a second local bitline connected to the non-program transistor.
2. The non-volatile memory cell of claim 1 , the channel-based processing component induces electron tunneling to or from a channel region of the one transistor to program or erase, respectively, the one transistor.
3. The non-volatile memory cell of claim 1 , the channel-based processing component is further configured to apply zero volts to a selected wordline of the parallel bitline semiconductor architecture and to float respective local source lines and local bitlines connected to transistors on the selected wordline to erase the transistors on the selected wordline.
4. The non-volatile memory cell of claim 1 , the channel-based processing component raises at least one of the plurality of wordlines other than the common wordline to a moderate program voltage to inhibit the programming.
5. The non-volatile memory cell of claim 4 , the moderate program voltage has a voltage value less than a program voltage applied to the common wordline and greater than ground voltage.
6. The non-volatile memory cell of claim 1 , the channel-based processing module:
obtains a selected transistor for read measurement;
sets a wordline voltage of the selected transistor to a read voltage; and
measures a charge level or threshold voltage (V T ) of the selected transistor to implement the read measurement.
7. The non-volatile memory cell of claim 6 , the channel-based processing module sets a wordline of the plurality of wordlines that is not connected with a gate of the selected transistor to a voltage of opposite polarity from the read voltage to facilitate the read measurement.
8. The non-volatile memory cell of claim 1 , the plurality of transistors comprise charge trap (CT) transistors.
9. The non-volatile memory cell of claim 8 , the CT transistors comprise CT-NOR transistors.
10. The non-volatile memory cell of claim 1 , wherein at least one of:
the plurality of transistors comprise at least one program state, or an erase state, having a negative gate voltage; or
the plurality of transistors comprise multi-layer cell (MLC) transistors.
11. The non-volatile memory device of claim 1 configured for use with a computer, a laptop, a personal digital assistant (PDA), a cellular telephone, a smartphone, or an electronic gaming device, or a combination thereof.
12. A method of processing a parallel bitline semiconductor architecture, comprising:
selecting a block of memory cells of the semiconductor architecture;
applying zero volts to respective ones of a pair of local bitlines directly connected to a source and drain, respectively, of a plurality of charge trap NOR transistors of the block of memory cells; and
applying a program voltage to a wordline connected to a gate of a selected one of the plurality of charge trap NOR transistors, and applying a moderate voltage smaller than the program voltage and greater than zero volts to a second wordline connected to non-selected one of the plurality of charge trap NOR transistors, to facilitate programming the selected one and inhibiting programming of the non-selected one of the plurality of charge trap NOR transistors.
13. The method of claim 12 , applying the program voltage further comprises increasing the wordline to ten or more volts above ground.
14. The method of claim 12 , further comprising floating a second pair of local bitlines connected to a source and drain, respectively, of the non-selected one of the plurality of charge trap NOR transistors to further facilitate the inhibiting programming.
15. The method of claim 12 , further comprising raising a well voltage of the block of memory cells to a high voltage.
16. The method of claim 15 , further comprising at least one of:
grounding all wordlines of the block of memory cells to erase all memory cells of the block of memory cells; or
grounding the wordline and raising the voltage of the second wordline to a moderate voltage to erase only cells connected to the wordline.
17. A system for processing a non-volatile memory cell, comprising:
means for selecting a block of memory cells comprising a target cell in a parallel bitline semiconductor architecture, the target cell being one of a plurality of cells having respective source nodes and respective drain nodes, the source nodes being connected directly to one of a pair of local bitlines and the drain nodes being connected directly to a second of the pair of local bitlines, the one of the pair of local bitlines is connected to a common source line by a first select transistor and the second of the pair of local bitlines is connected to a common data line by a second select transistor;
means for raising at least one of the pair of local bitlines to a higher voltage than applied to a substrate of the target cell;
means for raising a wordline of the target cell to a read voltage; and
means for mitigating current leakage in a second cell of the plurality of cells connected directly to the pair of local bitlines.
18. The system of claim 17 , further comprising at least one of:
means for lowering a second wordline connected to a gate of the second cell to a negative voltage to facilitate the mitigating current leakage; or
means for increasing a V T of the second cell to facilitate the mitigating current leakage.