Nonlinearity robust successive requantizer
View Patent ↗A successive requantizer, which serves as a replacement for a ΔΣ modulator in a fractional-N PLL or a DAC, and avoids spurious tone problems, thereby circumventing the tradeoffs that result from reliance on the common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. The successive requantizer performs digital quantization one bit at a time in such a way that the quantization noise can he engineered to have desirable properties such as non-linearity robustness. The successive requantizer is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers.
1. A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage generates a quantization sequence s d [n], with the property that x d [n]+s d [n] is an even number for each n, where x d [n] is the quantization stage's input sequence; and
each quantization stage adds s d [n] to x d [n].
2. The device of claim 1 , wherein each quantization stage discards a predetermined number of least significant bits to implement the quantization.
3. The device of claim 1 , wherein each quantization stage simultaneously divides its input by 2 b and quantizes the result by b bits every sample period
4. The device of claim 3 , wherein each quantization stage simultaneously halves its input and quantizes the result by one bit every sample period.
5. The device of claim 1 , wherein numbers within the successive requantizer device are integers with a two's-compliment binary number representation at each time n, and at each quantization stage s d [n] is chosen such that x d [n]+s d [n] does not exceed the range of a (K−d)-bit two's complement integer, and the parity of s d [n] is the same as that of x d [n], where K is determined by the number of quantization stages, the number of bits quantized per stage, and the logic which generates s d [n].
6. The device of claim 1 , wherein that the running sum of each s d [n] sequence, i.e.,
t
d
[
n
]
=
∑
k
=
0
n
s
d
[
k
]
,
is bounded for all n, and each s d [n] has a smooth power spectral density that increases monotonically with frequency.
7. The device of claim 6 , wherein t d [n] is a discrete-valued Markov random sequence conditioned on the parity of x d [n].
8. The device of claim 6 , wherein t d [n] is a random process whose autocorrelation function converges to a constant as its time spread increases.
9. The device of claim 6 , wherein each quantization stage calculates s d [n] as a function the running sum of t d [n] in addition to t d [n], an independent random sequence, and the parity of x d [n].
10. The device of claim 6 , wherein each quantization stage calculates s d [n] as a function of the previous value of t d [n], the parity of the current value of x d [n], and the current value of an independent random sequence.
11. The device of claim 1 , wherein each quantization stage implements
s
d
[
n
]
=
{
0
,
if
x
d
[
n
]
=
even
p
d
[
n
]
,
if
x
d
[
n
]
=
odd
and
t
d
[
n
-
1
]
=
0
,
1
,
if
x
d
[
n
]
=
odd
and
t
d
[
n
-
1
]
=
-
1
,
-
1
,
if
x
d
[
n
]
=
odd
and
t
d
[
n
-
1
]
=
1
,
can be used, where p d [n] is an independent random sequence that takes on the values 1 and −1 with equal probability.
12. The device of claim 1 , wherein that the running sums of each t d,i [n] sequence, i.e.,
t
d
,
i
[
n
]
=
∑
k
=
0
n
t
d
,
i
-
1
[
k
]
,
t
d
,
1
[
n
]
=
∑
k
=
0
n
t
d
[
n
]
are bounded for all n, and each t d,i [n] has a smooth power spectral density that increases monotonically with frequency.
13. A fractional-N PLL device, comprising:
a phase lock loop generating an output frequency from a voltage controlled oscillator based upon a low frequency reference voltage; and
a successive requantizer according to claim 1 for providing a sequence of integers to control a divider in the phase locked loop to settle to a desired fractional value.
14. The fractional-N PLL device of claim 12 , further comprising an adaptive phase noise cancellation path.
15. A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage adds a quantization sequence to the quantization stage's input sequence and the quantization sequence is a discrete-valued Markov random sequence conditioned on the parity of the input sequence.
16. A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage adds a quantization sequence to the quantization stage's input sequence and the quantization sequence is random process whose autocorrelation function converges to a constant as its time spread increases.