Inter-bus communication interface device and data security device
View Patent ↗There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device.
1. A data security device configured to perform processing for securing data, comprising:
a first bus;
a second bus;
a third bus;
a central processing unit (CPU), connected to the first bus, configured to control operation of the data security device;
a data-acquiring circuit, connected to the first bus, configured to acquire target data;
a cryptographic processing circuit, connected to the second bus and not connected to the first bus, configured to perform cryptographic processing;
an authentication processing circuit, connected to the third bus and not connected to the first bus, configured to perform authentication processing; and
a data input/output control circuit, connected to the first bus, connected to the cryptographic processing circuit via the second bus, and connected to the authentication processing circuit via the third bus, configured to control data transfer to and from the cryptographic processing circuit and the authentication processing circuit, independently of the CPU,
wherein the data input/output control circuit acquires the target data from the data-acquiring circuit via the first bus, stores the target data in an internal memory, inputs the stored target data to the cryptographic processing circuit via the second bus, acquires encrypted data as a result of execution of the cryptographic processing from the cryptographic processing circuit via the second bus, and inputs the encrypted data to the authentication processing circuit and acquires result data therefrom via the third bus.
2. The data security device as claimed in claim 1 , wherein the data input/output control circuit includes a direct memory access controller for data transfer over the first bus, and acquires the target data from the data-acquiring circuit by data transfer using Direct Memory Access.
3. The data security device as claimed in claim 1 , further comprising a memory device connected to the first bus, configured to store the target data which is acquired by the data-acquiring circuit,
wherein the data input/output control circuit obtains the target data from the memory device.
4. The data security device as claimed in claim 1 , wherein after storing the target data in the internal memory, the target data is divided into unit data elements each having a unit data length and serving as a unit for the cryptographic processing, and then inputted to the cryptographic processing circuit.
5. The data security device as claimed in claim 4 , wherein the internal memory is divided into at least two areas, and while the target data which is stored in a first area is being processed by the cryptographic processing circuit, next target data to be processed is stored in a second area.
6. The data security device as claimed in claim 5 , wherein the internal memory is divided into areas each having a unit storage capacity corresponding to the unit data length of the unit data elements for the cryptographic processing.
7. The data security device as claimed in claim 1 , wherein the data input/output control circuit inputs the target data which is sequentially provided through streaming, to the cryptographic processing circuit in an order that the target data is acquired, and outputs encrypted data upon completion of the execution of the cryptographic processing.
8. The data security device as claimed in claim 1 , wherein the cryptographic processing circuit detects a volume of the target data, and carries out the cryptographic processing on the target data when the volume of the target data reaches a predetermined value.
9. The data security device as claimed in claim 1 , wherein:
the cryptographic processing circuit is provided in plurality;
the data input/output control circuit is provided in plurality, the data input/output control circuits being respectively connected to the plurality of cryptographic processing circuits; and
the data input/output control circuits acquire the target data in a divided form, and input the divided target data to the corresponding cryptographic processing circuits in parallel with each other.
10. The data security device as claimed in claim 1 , wherein the internal memory is shared by the cryptographic processing circuit via the second bus and the authentication processing circuit via the third bus.
11. The data security device as claimed in claim 10 , wherein the data input/output control circuit divides the internal memory into a plurality of storage areas based on whether the internal memory is used for the cryptographic processing or for the authentication processing.
12. The data security device as claimed in claim 1 , wherein the data input/output control circuit includes a direct memory access controller for data transfer directly to and from a memory device, which is not connected to the first bus, using Direct Memory Access.
13. A data communication device configured to transmit secured data via a network, comprising:
a first bus;
a second bus;
a third bus;
a central processing unit (CPU), connected to the first bus, configured to generate transmit data;
a cryptographic processing circuit, connected to the second bus and not connected to the first bus, configured to encrypt data;
a communication circuit, connected to the first bus, configured to transmit data via the network;
an authentication processing circuit, connected to the third bus and not connected to the first bus, configured to perform authentication processing; and
a data input/output control circuit, connected to the first bus, connected to the cryptographic processing circuit via the second bus, and connected to the authentication processing circuit via the third bus, configured to control data transfer to and from the cryptographic processing circuit and the authentication processing circuit, independently of the CPU,
wherein the data input/output control circuit acquires the target data from the data acquiring circuit via the first bus, stores the target data in an internal memory, inputs the stored target data to the cryptographic processing circuit via the second bus, acquires encrypted data as a result of execution of the cryptographic processing from the cryptographic processing circuit via the second bus, and inputs the encrypted data to the authentication processing circuit and acquires result data therefrom via the third bus.
14. A data communication device configured to receive secured data via a network, comprising:
a first bus;
a second bus;
a third bus;
a central processing unit (CPU), connected to the first bus, configured to process receive data;
a cryptographic processing circuit, connected to the second bus and not connected to the first bus, configured to decrypt data;
a communication circuit, connected to the first bus, configured to acquire the receive data transmitted via the network;
an authentication processing circuit, connected to the third bus and not connected to the first bus, configured to perform authentication processing; and
a data input/output control circuit, connected to the first bus, connected to the cryptographic processing circuit via the second bus, and connected to the authentication processing circuit via the third bus, configured to control data transfer to and from the cryptographic processing circuit and the authentication processing circuit, independently of the CPU,
wherein the data input/output control circuit acquires the receive data from the communication circuit via the first bus, stores the receive data in an internal memory, inputs the stored receive data to the cryptographic processing circuit and acquires decrypted data therefrom via the second bus, inputs the decrypted data to the CPU via the first bus, and inputs authentication data to the authentication processing circuit and acquires therefrom result data for authentication via the third bus.