Integrated Schottky diode in high voltage semiconductor device
This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.
1. A semiconductor power device disposed in a semiconductor substrate of a first conductivity type with a drain disposed on a bottom surface wherein the power device comprises an active cell area and a termination area and wherein:
the active cell area comprises a plurality of transistor cells each having a planar gate comprises a patterned polysilicon segment disposed on a top surface of said semiconductor substrate;
each of the transistor cells further comprises a body region of a second conductivity type encompassing a source region of the first conductivity wherein the body region and the source region disposed below a top surface of the semiconductor substrate underneath and surrounding an outer peripheral of the gate segment;
the body region further includes a heavy body dopant region of the second conductivity type having a higher dopant concentration than the body region partially surrounding the source region and extended laterally below the top surface of the semiconductor substrate away from the gate segment; and
a Schottky metal disposed on top of the semiconductor substrate in contact with the body region, the heavy body dopant region and the source region to function as an internal Schottky diode integrated with the semiconductor power device.
2. The semiconductor power device of claim 1 wherein:
the termination area comprises a plurality of the patterned polysilicon segments each functioning as a field plate extending above a plurality of the body regions each encompassing the heavy body dopant region of the second conductivity type wherein the body regions functioning as guard rings and the heavy body dopant regions functioning as field plate contact regions each contacting the field plate.
3. The semiconductor power device of claim 1 further comprising:
shallow body-dopant regions disposed adjacent to the body regions immediately under said Schottky metal layer having a depth significantly shallower than said body regions.
4. The semiconductor power device of claim 1 wherein:
said semiconductor substrate comprises an N-type epitaxial layer for supporting said body-dopant regions of a P-type conductivity encompassing said source regions of the N-type conductivity in the active cell area.
5. The semiconductor power device of claim 1 wherein:
said semiconductor substrate comprises a P-type epitaxial layer for supporting said body-dopant regions of an N-type conductivity encompassing said source regions of the P-type conductivity in the active cell area.
6. The semiconductor power device of claim 1 wherein:
said semiconductor power device further comprises a MOSFET integrated with the internal Schottky diode.
7. The semiconductor power device of claim 1 wherein:
said semiconductor power device further comprises an N-channel MOSFET integrated with the internal Schottky diode supported on an N-type semiconductor substrate.
8. The semiconductor power device of claim 1 wherein:
said semiconductor power device further comprises a P-channel MOSFET integrated with the internal Schottky diode supported on a P-type semiconductor substrate.
9. The semiconductor power device of claim 1 wherein:
said semiconductor power device further comprises an insulate gate bipolar transistor (IGBT) integrated with the internal Schottky diode.
10. The semiconductor power device of claim 1 wherein:
said semiconductor power device further comprises an insulate gate bipolar transistor (IGBT) integrated with the internal Schottky diode supported on a N-type semiconductor substrate includes a P-type bottom layer with N-type dopant regions disposed near a bottom surface of said semiconductor substrate.
11. The semiconductor power device of claim 1 wherein:
said semiconductor substrate further comprises a superjunction region comprises alternating N-type and P-type dopant columns below said body regions.
12. The semiconductor power device of claim 1 wherein:
said semiconductor substrate further comprises a superjunction region disposed in a N-type semiconductor substrate comprises P-type columns and N-type columns disposed underneath said body regions.