Jitter evaluation
A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit ( 401 ) recovers a clock signal from the test signal and a synchronization circuit generates a synchronized system clock signal from said recovered clock signal. A sinusoid generator ( 403 ) generates a sinusoid signal from the synchronized system clock signal and a sampling analog to digital converter ( 404 ) samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator ( 401 ) is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier ( 412 ) is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values. Furthermore, a co-ordinate rotation device ( 416 ) is configured to receive said first product via a first low pass filter ( 414 ) and to receive said second product via a second low pass filter ( 415 ) to produce an output indicative of jitter phase.
1. Jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, comprising:
a clock recovery circuit configured to recover a recovered clock signal from said digital test signal;
a synchronisation circuit configured to generate a synchronised system clock signal from said recovered clock signal;
a sinusoid generator configured to generate a sinusoid signal from said synchronised system clock signal; and
a sampling analog to digital converter configured to sample said sinusoid signal by said recovered clock signal to provide sinusoid samples, further comprising:
a numerically controlled oscillator configured to produce sine values and cosine values in response to receiving said synchronised system clock signal;
a first multiplier configured to produce a first product of said sinusoid samples and said sine values;
a second multiplier configured to produce a second product of said sinusoid samples and said cosine values; and
a co-ordinate rotation device configured to receive said first product via a first low pass filter and to receive said second product via a second low pass filter, and to produce a phase signal that is indicative of jitter phase.
2. The apparatus as claimed in claim 1 , wherein said digital test signal is received via a device under test so as to evaluate the acceptability of said device under test.
3. The apparatus as claimed in claim 2 , wherein said device under test is a device for processing and/or transmitting high definition serial digital video data.
4. The apparatus as claimed in claim 1 , including a frequency divider for dividing the frequency of said recovered clock signal from a clock recovery circuit so as to supply a divided clock signal to said synchronisation circuit and a sampling analog to digital converter.
5. The apparatus as claimed in claim 1 , including sample and hold devices for evaluating peak-to-peak jitter for application to a display device.
6. A method of evaluating jitter, comprising the steps of:
recovering a clock signal from a digital input signal;
generating a synchronized system clock signal from said recovered clock signal;
generating a sinusoid signal from said synchronised system clock signal;
sampling said sinusoid signal by said recovered clock signal and providing sinusoid samples;
producing sine values and cosine values in response to receiving said synchronized system clock signal;
producing a first product of said sinusoid samples and said sine values;
producing a second product of sinusoid samples and said cosine values; and
producing a phase signal that is indicative of jitter phase by low pass filtering said first product and said second product, and supplying the resulting sine dependent and cosine dependent values to a co-ordinate rotation procedure.
7. The method as claimed in claim 6 , wherein the frequency of said recovered clock signal is divided to generate a divided clock signal.
8. The method as claimed in claim 6 , wherein peak-to-peak jitter is evaluated by receiving samples from sample and hold devices.
9. The apparatus as claimed in claim 1 , including a first high pass filter for receiving said output to evaluate timing jitter.
10. The apparatus as claimed in claim 1 , including a second high pass filter to evaluate alignment jitter.
11. The method as claimed in claim 6 , wherein timing jitter is evaluated by receiving said phase information via a first high pass filter.
12. The method as claimed in claim 6 , wherein alignment jitter is evaluated by receiving said phase signal via a second high pass filter.
13. The method of claim 6 , further comprising evaluating timing jitter by performing a first high pass filter operation on said phase signal, and evaluating alignment jitter by performing a second high pass filter operation on said phase signal.
14. The apparatus of claim 1 , further comprising a first high pass filter configured to receive said phase signal to evaluate timing jitter, and a second high pass filter configured to receive said phase signal to evaluate alignment jitter.