Semiconductor integrated circuit device and test terminal arrangement method

1. A semiconductor integrated circuit device, comprising:

first and second logic circuit cells provided at least at one corner part out of four corners of a chip of the semiconductor integrated circuit device,

each of the first and second logic circuit cells having a shape of a trapezoid in which a side facing an oblique side crosses each of a short side and a long side at a right angle, the first and second logic circuit cells being arranged with the oblique sides thereof facing to each other.

2. The semiconductor integrated circuit device according to claim 1 , including:

a first logic circuit cell column including a plurality of first logic circuit cells arranged in a line along a first side of the chip; and

a second logic circuit cell column including a plurality of second logic circuit cells arranged in a line along a second side of the chip orthogonal to the first side, the first side of the chip crossing the second side of the chip at the at the corner part, wherein

the first logic circuit cell provided at the corner part is arranged to have the long side thereof faced with a side of a cell at an end portion of the first logic circuit cell column,

the second logic circuit cell provided at the corner part is arranged to have the long side thereof faced with a side of a cell at an end portion of the second logic circuit cell column, and

the first and second logic circuit cells provided at the corner part have planar shapes symmetrical to each other with respect to a virtual line intermediate between the oblique sides thereof arranged opposite to each other.

3. The semiconductor integrated circuit device according to claim 1 , wherein each of the first logic circuit cell and the second logic circuit cell includes one of an input cell, an output cell, and an input/output cell.

4. The semiconductor integrated circuit device according to claim 1 , wherein each of the first logic circuit cell and the second logic circuit cell includes a test logic circuit cell connected to a test terminal.

5. The semiconductor integrated circuit device according to claim 4 , comprising:

a plurality of peripheral test wirings arranged on a metal interconnect layer in a region around the chip, with a width corresponding to a length of the long side of each of the first logic circuit cell and the second logic circuit cell comprising the test logic circuit cell.

6. The semiconductor integrated circuit device according to claim 5 , wherein the plurality of peripheral test wirings are respectively connected to connecting portions within regions of the first logic circuit cell and the second logic circuit cell located immediately below the plurality of peripheral test wirings at the corner part through conductive members.

7. A method for arranging test terminals in a semiconductor integrated circuit device, the method comprising:

arranging first and second test logic circuit cells at least at one corner out of four corners of a chip of the semiconductor integrated circuit device, each of the first and second logic circuit cells having a shape of a trapezoid in which a side facing an oblique side crosses each of a short side and a long side at a right angle, the first and second logic circuit cells being arranged with the oblique sides thereof facing to each other; and

connecting each of the first and second test logic circuit cells to a test pad.

8. The method according to claim 7 , comprising:

arranging a first logic circuit cell column including a plurality of first logic circuit cells in a line along a first side of the chip; and

arranging a second logic circuit cell column including a plurality of second logic circuit cells in a line along a second side of the chip orthogonal to the first side, the first side of the chip crossing the second side of the chip at the at the corner part,

arranging the first logic circuit cell at the corner part to have the long side thereof faced with a side of a cell at an end portion of the first logic circuit cell column, and

arranging the second logic circuit cell at the corner part to have the long side thereof faced with a side of a cell at an end portion of the second logic circuit cell column,

the first and second logic circuit cells provided at the corner part having planar shapes symmetrical to each other with respect to a virtual line intermediate between the oblique sides thereof arranged opposite to each other.

9. The method according to claim 7 , wherein each of the first logic circuit cell and the second logic circuit cell includes one of an input cell, an output cell, and an input/output cell.

10. The method according to claim 7 , comprising

arranging a plurality of peripheral test wirings on a metal interconnect layer in a region around the chip, with a width corresponding to a length of the long side of each of the first test logic circuit cell and the second test logic circuit cell.

11. The method according to claim 10 , comprising

connecting the plurality of peripheral test wirings respectively connected to connecting portions within regions of the first logic circuit cell and the second logic circuit cell located immediately below the plurality of peripheral test wirings at the corner part through conductive members.