Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method

1. A synchronization detection circuit comprising:

a multiphase clock generation circuit which comprises a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which generates high-speed multiphase clock signals having a frequency obtained by multiplying a frequency of the reference clock signal, and low-speed multiphase clock signals having a frequency obtained by dividing a frequency of the high-speed multiphase clock signals; and

a synchronous clock specifying circuit that specifies a clock signal synchronized with a synchronous signal from among the multiphase clock signals, and generates a synchronous position signal indicating a synchronous position of the synchronous signal, based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and representative clock signals selected from the low-speed multiphase clock signals.

2. The synchronization detection circuit according to claim 1 , wherein the phase locked loop circuit comprises:

a multiplier circuit that performs multiplication processing on clock signals;

a phase interpolation circuit that performs phase interpolation on clock signals; and

a frequency dividing circuit that performs frequency division processing on clock signals.

3. The synchronization detection circuit according to claim 1 , wherein the synchronous clock specifying circuit comprises:

a high-speed clock comparator that compares a pulse edge of the synchronous signal with a pulse edge of the high-speed multiphase clock signals;

a representative clock comparator that compares a pulse edge of the synchronous signal with a pulse edge of the representative clock signals;

a high-speed clock encoder that generates a high-speed clock specifying signal for specifying a clock signal synchronized with the synchronous signal from among the high-speed multiphase clock signals, based on a comparison result from the high-speed clock comparator;

a representative clock signal encoder that generates a representative clock specifying signal for specifying a clock signal corresponding to the synchronous signal from among the representative clock signals, based on a comparison result from the representative clock comparator; and

a synchronous position signal generation circuit that generates the synchronous position signal based on the high-speed clock specifying signal and the representative clock specifying signal.

4. The synchronization detection circuit according to claim 1 , further comprising a delay prevention circuit that generates a delay synchronous signal in consideration of a predetermined delay with respect to the synchronous signal, and a delay synchronous position signal indicating a synchronous position of the delay synchronous signal, and holds the synchronous position signal and the delay synchronous position signal.

5. The synchronization detection circuit according to claim 4 , wherein

the delay prevention circuit generates a delay composite synchronous signal having two pulse edges of the synchronous signal and the delay synchronous signal, and

the synchronous clock specifying circuit compares the delay composite synchronous signal with the multiphase clock signals.

6. A pulse width modulation circuit which comprises a synchronization detection circuit according to claim 1 , and which outputs a pulse width modulation signal based on multiphase clock signals generated by the multiphase clock generation circuit, a synchronous position signal generated by the synchronous clock specifying circuit, and digital pulse data.

7. The pulse width modulation circuit according to claim 6 , wherein the multiphase clock signals correspond to the low-speed multiphase clock signals.

8. A synchronization detection method comprising:

generating high-speed multiphase clock signals synchronized in phase with a reference clock signal, having a frequency obtained by multiplying a frequency of the reference clock signal, and having a plurality of different phases;

generating low-speed multiphase clock signals synchronized in phase with the reference clock signal, having a frequency obtained by dividing a frequency of the high-speed multiphase clock signals, and having a plurality of different phases;

selecting a representative clock signal capable of specifying a cycle of each of the high-speed multiphase clock signals from among the low-speed multiphase clock signals;

comparing a synchronous signal with the high-speed multiphase clock signals;

comparing the synchronous signal with the representative clock signal; and

generating a synchronous position signal for specifying a synchronous position of the synchronous signal based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and the representative clock signal.