Semiconductor device

1. A semiconductor device, comprising:

an element isolation film formed in a semiconductor layer, the element isolation film defining an element formation region;

a gate electrode formed above the element formation region, the gate electrode having ends respectively extending above the element isolation film; and

a source region and a drain region which are formed in the element formation region to sandwich therebetween a channel formation region under the gate electrode,

wherein the gate electrode comprises at each of the ends thereof a high work function region in which a work function is higher than a work function in other regions over at least a part of an interface between the element formation region and the element isolation film,

wherein the semiconductor layer located in the channel formation region is of a first conductivity type;

wherein the gate electrode is of a second conductivity type,

wherein the high work function region comprises a region of the first conductivity type which is formed in a part of the gate electrode and is located over the interface, and

wherein the gate electrode comprises:

a semiconductor pattern of the second conductivity type;

the region of the first conductivity type which is formed in the semiconductor pattern and which comprises the high work function region; and

a conductive layer formed over the semiconductor pattern.

2. A semiconductor device according to claim 1 , wherein the region of the first conductivity type faces neither the source region nor the drain region.

3. A semiconductor device according to claim 1 , further comprising:

parasitic transistor regions formed in the interface between the element formation region and the element isolation film.

4. A semiconductor device according to claim 3 , wherein the parasitic transistor regions are positioned under the gate electrode.

5. A semiconductor device according to claim 3 , wherein the high work function region is formed over the parasitic transistor regions.

6. A semiconductor device according to claim 3 , wherein, in a direction in which the gate electrode extends, the high work function region is formed before and beyond edges of the parasitic transistor regions.

7. A semiconductor device according to claim 1 , wherein the first conductivity type is different from the second conductivity type.

8. A semiconductor device according to claim 1 , wherein regions of the gate electrode that face the source region and the drain region are of the second conductivity type.

9. A semiconductor device according to claim 1 , wherein the semiconductor pattern comprises a polysilicon pattern that abuts side surfaces of the high work function region.

10. A semiconductor device according to claim 9 , wherein the conductive layer abuts an upper surface of the high work function region.

11. A semiconductor device according to claim 10 , wherein the conductive layer further abuts an upper surface of the polysilicon pattern.

12. A semiconductor device according to claim 11 , wherein the conductive layer comprises a silicide layer.

13. A semiconductor device according to claim 12 , wherein the polysilicon pattern is disposed between the conductive layer and the element isolation film.

14. A semiconductor device according to claim 13 , wherein, in a plan view, an entirety of an upper surface of the element isolation film overlaps with the polysilicon pattern and the high work function region.