Inverter, method of operating the same and logic circuit comprising inverter

1. An inverter comprising:

a load transistor; and

a driving transistor connected to the load transistor,

wherein one of the load transistor and the driving transistor has a double gate structure, and the other of the load transistor and the driving transistor has a single gate structure.

2. The inverter of claim 1 , wherein the load transistor is a depletion mode transistor, and the driving transistor is an enhancement mode transistor having the double gate structure.

3. The inverter of claim 1 , wherein the load transistor is a depletion mode transistor having the double gate structure, and the driving transistor is an enhancement mode transistor.

4. The inverter of claim 1 , wherein the load transistor and the driving transistor are oxide thin film transistors (TFTs).

5. The inverter of claim 4 , wherein the load transistor and the driving transistor include channel layers made of a ZnO-based oxide.

6. The inverter of claim 1 , wherein the load transistor and the driving transistor are a top gate transistor, and

one of the load transistor and the driving transistor further includes a bottom gate under the top gate transistor.

7. The inverter of claim 6 , wherein the load transistor and the driving transistor include an active layer having a channel region, a source region, and a drain region.

8. The inverter of claim 6 , wherein the load transistor and the driving transistor include a channel layer, a source layer contacting a first end of the channel layer, and a drain layer contacting a second end of the channel layer.

9. The inverter of claim 1 , wherein each of the load transistor and the driving transistor are a bottom gate transistor, and

one of the load transistor and the driving transistor further includes a top gate above the bottom gate transistor.

10. The inverter of claim 1 , wherein the gates of the double gate structure in either the load transistor or the driving transistor are separated from each other.

11. The inverter of claim 1 , wherein the gates of the double gate structure in either the load transistor or the driving transistor are electrically connected to each other.

12. A logic circuit comprising:

a plurality of the inverters of claim 1 .

13. The logic circuit of claim 12 , wherein the load transistor and the driving transistor of each of the plurality of inverters are a top gate transistor and one of the load transistor and the driving transistor further includes a bottom gate below the top gate transistor, the bottom gate being separated from the corresponding top gate, and

the bottom gate of each of the plurality of inverters are electrically connected to one another.

14. The logic circuit of claim 12 , wherein the load transistor and the driving transistor of each of the plurality of inverters is a bottom gate transistor and one of the load transistor and the driving transistor further includes a top gate above the bottom gate transistor, the top gate being separated from the corresponding bottom gate, and

the top gate of each of the plurality of inverters are electrically connected to one another.

15. The logic circuit of claim 12 , wherein the logic circuit includes at least one of a NAND circuit, a NOR circuit, an encoder, a decoder, a multiplexer (MUX), a demultiplexer (DEMUX), and a sense amplifier.

16. An inverter comprising:

a load transistor; and

a driving transistor connected to the load transistor,

wherein one of the load transistor and the driving transistor has a double gate structure and the other of the load transistor and the driving transistor has a single gate structure, and

wherein a threshold voltage of the one of the load and the driving transistor having the double gate structure is changed by at least one of two gates of the double gate structure and is different from a threshold voltage of the other of the load and the driving transistor having the single gate structure.

17. The inverter of claim 16 , wherein the load transistor is a depletion mode transistor, and the driving transistor is an enhancement mode transistor having the double gate structure.

18. The inverter of claim 16 , wherein the load transistor is a depletion mode transistor having the double gate structure, and the driving transistor is an enhancement mode transistor.

19. The inverter of claim 16 , wherein the load transistor and the driving transistor are oxide thin film transistors (TFTs).

20. The inverter of claim 19 , wherein the load transistor and the driving transistor include channel layers made of a ZnO-based oxide.

21. The inverter of claim 16 , wherein the load transistor and the driving transistor are a top gate transistor, and

one of the load transistor and the driving transistor further includes a bottom gate under the top gate transistor.

22. The inverter of claim 21 , wherein the load transistor and the driving transistor include an active layer having a channel region, a source region, and a drain region.

23. The inverter of claim 21 , wherein the load transistor and the driving transistor include a channel layer, a source layer contacting a first end of the channel layer, and a drain layer contacting a second end of the channel layer.

24. The inverter of claim 16 , wherein each of the load transistor and the driving transistor are a bottom gate transistor, and

one of the load transistor and the driving transistor further includes a top gate above the bottom gate transistor.

25. The inverter of claim 16 , wherein the gates of the double gate structure in either the load transistor or the driving transistor are separated from each other.

26. The inverter of claim 16 , wherein the gates of the double gate structure in either the load transistor or the driving transistor are electrically connected to each other.