Method of making a diode read/write memory cell in a programmed state

1. A method of making a diode, comprising:

forming a first electrode;

forming a semiconductor region in electrical contact with the first electrode, wherein the semiconductor region comprises a p-n or a p-i-n junction in at least one silicon, germanium or silicon-germanium layer;

forming a titanium layer on the semiconductor region;

forming a titanium nitride layer on the titanium layer;

reacting the titanium layer with the semiconductor region to form a titanium silicide, titanium germanide, or titanium silicide-germanide layer on the semiconductor region;

removing the titanium nitride layer and a remaining portion of the titanium layer after the step of reacting; and

forming a second electrode in electrical contact with the titanium silicide, titanium germanide or titanium silicide-germanide layer.

2. The method of claim 1 , wherein the step of forming the semiconductor region comprises:

depositing a first silicon, germanium or silicon-germanium layer of a first conductivity type over the first electrode;

forming a second intrinsic silicon, germanium or silicon-germanium layer on the first layer; and

implanting dopants of a second conductivity type into the second layer to form a third layer of a second conductivity type opposite to the first conductivity type to form a p-i-n diode.

3. The method of claim 1 , further comprising patterning the semiconductor region such that the semiconductor region has a substantially cylindrical shape.

4. The method of claim 3 , further comprising:

forming an insulating layer over the substantially cylindrical semiconductor region prior to the step of reacting; and

planarizing the insulating layer such that it surrounds the semiconductor region.

5. The method of claim 1 , wherein:

the step of forming the semiconductor region comprises forming an amorphous or polycrystalline semiconductor region; and

further comprising crystallizing the semiconductor region to form a low resistivity polycrystalline semiconductor region using the titanium silicide, titanium germanide or titanium silicide-germanide layer as a crystallization template.

6. The method of claim 1 , wherein the first electrode, the diode and the second electrode form a complete memory cell of a memory device.

7. The method of claim 6 , wherein the diode comprises a p-i-n diode which is fabricated in a stable low resistivity, programmed state corresponding to a first memory state of the memory cell without performing an electrical programming step.

8. The method of claim 7 , wherein the diode is fabricated in the low resistivity programmed state by crystallizing an amorphous or polycrystalline semiconductor region.

9. The method of claim 7 , further comprising:

applying a reverse bias greater than a predetermined critical voltage value to the diode to switch the diode to a stable high resistivity, unprogrammed state corresponding to a second memory state of the memory cell; and

applying a forward bias to the diode to switch the diode to the low resistivity, programmed state.

10. The method of claim 1 , further comprising monolithically forming at least one additional device level over the diode.