Semiconductor device having delay control circuit
View Patent ↗A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.
1. A semiconductor device, comprising:
a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
a first delay circuit having a plurality of first delay elements connected in series;
a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits; and
a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit,
wherein the first delay elements and the second delay elements differ from each other in a fan-out.
2. The semiconductor device as claimed in claim 1 , wherein the first delay elements and the second delay elements differ from each other in a change of a delay amount due to PVT (process, voltage, and temperature) variation.
3. The semiconductor device as claimed in claim 2 , wherein the first delay elements and the second delay elements differ from each other in an operation voltage.
4. The semiconductor device as claimed in claim 1 , wherein an operation voltage of the first delay elements is higher than an operation voltage of the second delay elements, and a fan-out of the first delay elements is smaller than a fan-out of the second delay elements.
5. The semiconductor device as claimed in claim 4 , wherein the delay control circuit includes a third delay circuit having a plurality of third delay elements connected in series, and the first delay elements and the third delay elements are the same in an operation voltage and a fan-out.
6. The semiconductor device as claimed in claim 5 , wherein
the setting circuit sets to increase the delay amount of the delay control circuit as the propagation speed of the pulse signal propagating through the second delay circuit is faster than the propagation speed of the pulse signal propagating through the first delay circuit, and
the setting circuit sets to decrease the delay amount of the delay control circuit as the propagation speed of the pulse signal propagating through the second delay circuit is slower than the propagation speed of the pulse signal propagating through the first delay circuit.
7. The semiconductor device as claimed in claim 1 , wherein the pulse signal is generated intermittently.
8. A semiconductor device, comprising:
a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
a first delay circuit having a plurality of first delay elements connected in series;
a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits;
a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit;
a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each arranged at an associated one of intersections of the word lines and the bit lines;
a word driver that selects any one of the word lines; and
a plurality of sense amplifiers each connected to corresponding one of the bit lines, wherein
the reference signal is a signal synchronized with an activation timing of the word driver, and
the operation timing signal is a signal for activating the sense amplifiers.
9. The semiconductor device as claimed in claim 8 , wherein the memory cell is a DRAM (Dynamic Random Access Memory) cell, and the pulse signal is generated in response to at least an issuance of a refresh command.
10. A semiconductor device, comprising:
a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
a first delay circuit having a plurality of first delay elements connected in series;
a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits;
a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit;
a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each arranged at an associated one of intersections of the word lines and the bit lines;
a word driver that selects any one of the word lines;
a plurality of sense amplifiers each connected to corresponding one of the bit lines; and
a column switch that selects any one of the sense amplifiers, wherein
the reference signal is a signal synchronized with an activation timing of the word driver, and
the operation timing signal is a signal for activating the column switch.
11. The semiconductor device as claimed in claim 10 , wherein the memory cell is a DRAM (Dynamic Random Access Memory) cell, and the pulse signal is generated in response to at least an issuance of a refresh command.