Panel structure including transistor and connecting elements, display device including the same, and methods of manufacturing panel structure and display device
Provided may be a panel structure, a display device including the panel structure, and methods of manufacturing the panel structure and the display device. Via holes for connecting elements of the panel structure may be formed by performing one process. For example, via holes for connecting a transistor and a conductive layer spaced apart from the transistor may be formed by performing only one process.
1. A panel structure comprising:
a first thin film transistor (TFT) including a first gate electrode, a first active layer, a first source electrode contacting the first active layer, and a first drain electrode contacting the first active layer;
a first conductive layer disposed apart from the first drain electrode;
a pixel electrode;
a first connection wire formed of a same material as the pixel electrode and disposed apart from the pixel electrode, the first connection wire including a first end and a second end;
a first conductive plug connecting the first drain electrode and the first end of the first connection wire; and
a second conductive plug connecting the second end of the first connection wire and the first conductive layer;
a second conductive layer spaced apart from the first conductive layer;
a third conductive layer spaced apart from the second conductive layer; and
a second connection wire formed of the same material as the first connection wire and the pixel electrode, the second connection wire including a first end connected to the second conductive layer and a second end connected to the third conductive layer.
2. The panel structure of claim 1 , wherein the first connection wire and the pixel electrode include at least one of a metal oxide and a metal, and the metal oxide is any one of indium tin oxide (ITO), indium zinc oxide (IZO), Sn oxide, In oxide, Zn oxide, and a mixture thereof.
3. The panel structure of claim 1 , further comprising:
a gate insulating layer covering the first conductive layer; and
an insulating layer on the gate insulating layer covering the first drain electrode,
wherein the first connection wire is on the insulating layer, and
wherein the first conductive plug penetrates the insulating layer, and the second conductive plug penetrates the gate insulating layer and the insulating layer.
4. The panel structure of claim 1 , wherein the second conductive layer is a power source line.
5. The panel structure of claim 1 , wherein the first conductive layer is a second gate electrode and the third conductive layer is a second source electrode, and
the panel structure further comprises:
a gate insulating layer covering the first gate electrode and the second gate electrode;
a second active layer on the gate insulating layer;
a second drain electrode contacting the second active layer; and
an insulating layer on the gate insulating layer covering the first active layer, the first source electrode, the first drain electrode, the second active layer, the second source electrode, and the second drain electrode.
6. The panel structure of claim 5 , wherein at least a portion of the second gate electrode is between the first gate electrode and the second conductive layer.
7. The panel structure of claim 5 , wherein the gate insulating layer covers the second conductive layer, and the second connection wire is on the insulating layer formed on the second conductive layer.
8. The panel structure of claim 5 , wherein the second source electrode extends over the second conductive layer, and
the panel structure further comprises:
a third conductive plug connecting the first end of the second connection wire to the second conductive layer by penetrating the gate insulating layer and the insulating layer, and
a fourth conductive plug connecting the second end of the second connection wire to the second source electrode by penetrating the insulating layer.
9. The panel structure of claim 5 , wherein the pixel electrode is formed on the insulating layer and connected to the second drain electrode.
10. The panel structure of claim 5 , wherein the pixel electrode is formed on the insulating layer between the second gate electrode and the second conductive layer.
11. The panel structure of claim 5 , wherein the second gate electrode, the second active layer, the second source electrode, and the second drain electrode form a second TFT, and the first TFT is a switching transistor, the second TFT is a driving transistor, and a part of the second gate electrode, a part of the second source electrode corresponding to the part of the second gate electrode, and the gate insulating layer therebetween operate as a capacitor.
12. The panel structure of claim 5 , wherein the first active layer is formed of at least one of amorphous silicon (a-Si), poly-crystalline silicon (poly-Si), GeSi, GaAs, and a metal oxide semiconductor.
13. The panel structure of claim 12 , wherein the second active layer is formed of a material that is the same as the material used to form the first active layer.
14. The panel structure of claim 1 , further comprising:
a second thin film transistor (TFT) including a drain electrode connected to the pixel electrode.
15. The panel structure of claim 14 , wherein the drain electrode of the second TFT and the pixel electrode are connected through a conductive plug formed integral with the pixel electrode.
16. The panel structure of claim 14 , wherein the first conductive layer is a gate electrode of the second TFT.
17. The panel structure of claim 14 , wherein the first TFT is a switching transistor and the second TFT is a driving transistor.
18. The panel structure of claim 1 , wherein the first connection wire and the pixel electrode are formed on a same layer.
19. A display device comprising the panel structure of claim 1 .
20. A panel structure comprising:
a first thin film transistor (TFT) including a first gate electrode, a first active layer, a first source electrode contacting the first active layer, and a first drain electrode contacting the first active layer;
a first conductive layer disposed apart from the first drain electrode;
a pixel electrode;
a first connection wire formed of a same material as the pixel electrode and disposed apart from the pixel electrode, the first connection wire including a first end and a second end;
a first conductive plug connecting the first drain electrode and the first end of the first connection wire; and
a second conductive plug connecting the second end of the first connection wire and the first conductive layer,
wherein the first connection wire and the pixel electrode include at least one of a metal oxide and a metal, and the metal oxide is any one of indium tin oxide (ITO), indium zinc oxide (IZO), Sn oxide, In oxide, Zn oxide, and a mixture thereof.
21. A display device comprising the panel structure of claim 20 .
22. A panel structure comprising:
a first thin film transistor (TFT) including a first gate electrode, a first active layer, a first source electrode contacting the first active layer, and a first drain electrode contacting the first active layer;
a first conductive layer disposed apart from the first drain electrode;
a pixel electrode;
a first connection wire formed of a same material as the pixel electrode and disposed apart from the pixel electrode, the first connection wire including a first end and a second end;
a first conductive plug connecting the first drain electrode and the first end of the first connection wire;
a second conductive plug connecting the second end of the first connection wire and the first conductive layer;
a gate insulating layer covering the first conductive layer; and
an insulating layer on the gate insulating layer covering the first drain electrode,
wherein the first connection wire is on the insulating layer, and
wherein the first conductive plug penetrates the insulating layer, and the second conductive plug penetrates the gate insulating layer and the insulating layer.
23. A display device comprising the panel structure of claim 22 .