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App. No. 12/588,362 · Confirmation No. 4322

Regulator circuit having N-type MOS transistor controlled by error amplifier

Inventor: Takashi Yamada
Abandoned -- Failure to Respond to an Office Action View Publication ↗
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2013-01-08 ABN Abandonment 2 View
2012-06-18 CTNF Non-Final Rejection 10 View
2012-06-18 892 List of references cited by examiner 1 View
2012-06-18 SRFW Search information including classification, databases and other search related notes 1 View
2012-06-18 1449 List of References cited by applicant and considered by examiner 1 View
2012-06-18 BIB Bibliographic Data Sheet 1 View
2012-06-18 SRNT Examiner's search strategy and results 8 View
2010-05-13 NTC.PUB Notice of Publication 1 View
2009-11-12 PD.FILED.E Priority Documents electronically retrieved by USPTO from a participating IP Office 16 View
2009-11-03 APP.FILE.REC Filing Receipt 3 View
2009-10-13 TRNA Transmittal of New Application 8 View
2009-10-13 SPEC Specification 13 View
2009-10-13 CLM Claims 3 View
2009-10-13 ABST Abstract 1 View
2009-10-13 OATH Oath or Declaration filed 2 View
2009-10-13 DRW Drawings-only black and white line drawings 4 View
2009-10-13 TRAN.LET Transmittal Letter 1 View
2009-10-13 IDS Information Disclosure Statement (IDS) Form (SB08) 1 View
2009-10-13 FOR Foreign Reference 25 View
2009-10-13 FOR Foreign Reference 13 View
2009-10-13 FOR Foreign Reference 9 View
2009-10-13 WFEE Fee Worksheet (SB06) 1 View
2009-10-13 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
12/588,362
Filed
2009-10-13
Pub. No.
US20100117611A1
Art Unit
2838