Power semiconductor device including gate lead-out electrode
View Patent ↗Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are arranged and a gate finger region different from a region where the cell region is formed. In the cell region, a gate electrode formed of a polysilicon (first conductive material) is formed. A polysilicon layer formed indivisibly with the gate electrode is formed in the gate finger region. An adhesion metal layer and a wiring metal layer are formed above the polysilicon layer by a lift-off method. The gate lead-out electrode is formed of a laminate structure including the polysilicon layer, the adhesion metal layer, and the wiring metal layer. A single layer of interlayer insulation film covering them is formed, on which a source electrode is formed.
1. A semiconductor device comprising:
a substrate containing a cell region in which a plurality of transistor cells are arranged;
a gate electrode formed in the cell region above the substrate and made of a first conductive material;
a gate lead-out electrode formed in a gate finger region different from the cell region and composed of a laminate structure including a first layer made of the first conductive material and a wiring metal layer formed on the first layer;
an interlayer insulation film composed of a single layer and covering the gate electrode and the gate lead-out electrode; and
a source electrode formed above the interlayer insulation film,
wherein the entire surface area of the wiring metal layer that is facing towards the gate electrode is bonded to the first layer without intervening an interlayer insulation film.
2. The semiconductor device according to claim 1 , wherein
the first conductive material is polysilicon.
3. The semiconductor device according to claim 1 , wherein
the gate lead-out electrode further comprises an adhesion metal layer disposed between the first layer and the wiring metal layer in contact therewith, an entire area of the adhesion metal layer is bonded between the first layer and the wiring metal layer.
4. The semiconductor device according to claim 3 , wherein
the adhesion metal layer has a pattern identical with that of the wiring metal layer.
5. The semiconductor device according to claim 1 , wherein
the gate electrode is formed indivisibly with the first layer of the gate lead-out electrode.
6. The semiconductor device according to claim 3 , wherein
the adhesion metal layer is a laminate film comprising a titanium nitride film and a titanium film.
7. The semiconductor device according to claim 1 , wherein
the resistivity of the wiring metal layer is lower than the resistivity of the first conductive material.
8. The semiconductor device according to claim 1 , wherein
the wiring metal layer comprises at least one of aluminum, cupper and tungsten.
9. The semiconductor device according to claim 1 , wherein
the source electrode is formed over the entire surface above the cell region and the gate lead-out electrode when viewed as a plan.
10. The semiconductor device according to claim 1 , wherein
the gate electrode has a trench gate structure.
11. The semiconductor device according to claim 1 , wherein
the interlayer insulation film is a laminate film composed of a plurality of different materials.
12. The semiconductor device according to claim 11 , wherein
the interlayer insulation film comprises a non-doped silicate glass film and a boron phosphorous silicate glass film formed in a layer thereabove.