Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path

1. A semiconductor integrated circuit device, comprising:

a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;

a delay detection unit that detects respective delay times in the plurality of delay paths; and

a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path,

wherein the plurality of delay paths are each configured to include an active circuit that operates upon receiving a power supply, and wherein the control unit stops supplying the power supply to the active circuits in the delay paths other than the selected one delay path during a normal operation.

2. The semiconductor integrated circuit device according to claim 1 ,

wherein each active circuit comprises a combinational logic circuit.

3. A semiconductor integrated circuit device, comprising:

a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;

a delay detection unit that detects respective delay times in the plurality of delay paths; and

a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path,

wherein the control unit selects, as one delay path, a delay path whose delay time is a minimum value among the plurality of delay paths.

4. The semiconductor integrated circuit device according to claim 3 , wherein the delay detection unit includes two registers different in latch timing from each other in correspondence with the plurality of delay paths, respectively, and wherein the control unit selects one delay path based on a delay time order in the plurality of delay paths, which are obtained based on latch data of the two registers in a case where the latch timing is changed.

5. The semiconductor integrated circuit device according to claim 4 , wherein one of the two registers operates in the latch timing of the clock signal during a normal operation.

6. A semiconductor integrated circuit device, comprising:

a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;

a delay detection unit that detects respective delay times in the plurality of delay paths; and

a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path,

wherein each delay path comprises a logic circuit operating complementarily, during detection of the delay time by the delay detection unit.