Liquid crystal display panel
A liquid crystal display panel capable of reducing a capacitance of a parasitic capacitor between a data line and a pixel electrode. The liquid crystal display panel comprises: a thin film transistor at a crossing of a gate line and a data line, liquid crystal cells including a pixel electrode connected to the thin film transistor; first shield patterns in the liquid crystal cells, each shield pattern being parallel to the data line without overlapping the data line, wherein the shield patterns are insulated from and overlap with an outer portion of the pixel electrode; and a common line arrayed to connect the shield patterns for each the liquid crystal cell.
1. A liquid crystal display panel, comprising:
a thin film transistor at a crossing of a gate line and a data line,
liquid crystal cells including a pixel electrode connected to the thin film transistor;
first shield patterns in the liquid crystal cells, each shield pattern being parallel to the data line without overlapping the data line, wherein the shield patterns are insulated from and overlap an outer portion of the pixel electrode;
a common line arranged to connect the shield patterns for each of the liquid crystal cells;
wherein the common line crosses the pixel electrode; and
a second shield pattern, the second shield pattern connected to the first shield patterns, wherein the second shield pattern is parallel to the gate line without overlapping the gate line and overlapped with the outer portion of the pixel electrode.
2. The liquid crystal display panel according to claim 1 , further comprising a storage capacitor arranged at an overlapping part of the first shield patterns and the pixel electrode and at an overlapping part of the common line and the pixel electrode.
3. The liquid crystal display panel according to claim 2 , wherein the common line further includes an expanded part whose line width is enlarged at a portion of the overlapping part of the common line and the pixel electrode.