Semiconductor device and connection checking method for semiconductor device
View Patent ↗Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.
1. A semiconductor device comprising:
a package substrate;
a semiconductor chip mounted on the package substrate;
a first land formed in a first principal surface of the package substrate;
a second land formed in a second principal surface of the package substrate;
a first connection terminal connected to the second land, and not electrically connected to the semiconductor chip;
a connection interconnection connected to the first land and the second land;
a second connection terminal formed in the second principal surface of the package substrate; and
a branch interconnection connected to the connection interconnection and the second connection terminal,
wherein the second connection terminal is connected to the first land and the second land and is not connected to other lands in the first principal surface of the package substrate, and
the second principal surface of the package substrate is opposed to the first principal surface of the package substrate.
2. The semiconductor device according to claim 1 , wherein the first and second connection terminals comprise solder balls.
3. The semiconductor device according to claim 1 , wherein the second connection terminal is arranged in a vacant area in the package substrate.
4. The semiconductor device according to claim 1 , wherein the second connection terminal is arranged in a same quadrant where the first connection terminal is arranged.
5. The semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the first principal surface of the package substrate.
6. The semiconductor device according to claim 1 , wherein the semiconductor chip is mounted inside the package substrate.
7. The semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the second principal surface of the package substrate.
8. The semiconductor device according to claim 1 , further comprising a third land formed in the second principal surface of the package substrate.
9. The semiconductor device according to claim 8 , wherein the third land is connected to the connection interconnection through the branch interconnection.
10. The semiconductor device according to claim 8 , wherein the third land is connected to the second connection terminal.
11. The semiconductor device according to claim 1 , wherein the first connection terminal and the second connection terminal are formed in a same surface of the package substrate.
12. The semiconductor device according to claim 1 , wherein the first connection terminal is formed in the second principal surface of the package substrate.
13. The semiconductor device according to claim 1 , wherein the semiconductor device comprises a ball grid array (BGA) type semiconductor device.