PLL circuit and method of controlling the same
View Patent ↗A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability.
1. A PLL circuit comprising:
a phase frequency detector that detects a phase difference between a reference signal and a feedback signal;
a filter circuit that outputs a control voltage based on an output signal from the phase frequency detector;
a voltage control oscillation circuit that controls a frequency of a clock signal output based on the control voltage;
a frequency dividing circuit that divides the frequency of the clock signal and outputs the feedback signal; and
an automatic adjustment circuit that adjusts a frequency division ratio of the frequency dividing circuit based on the control voltage,
wherein the automatic adjustment circuit comprises:
a comparison circuit that outputs a first control signal for controlling the frequency division ratio based on a potential difference between the control voltage and a first reference voltage, and outputs a second control signal for controlling the first reference voltage based on the potential difference between the control voltage and the first reference voltage; and
a reference voltage selection circuit that selects the first reference voltage based on the second control signal and outputs the first reference voltage selected.
2. The PLL circuit according to claim 1 , wherein
the comparison circuit outputs the first control signal and the second control signal based on a potential difference between the control voltage and a second reference voltage as well as on the potential difference between the control voltage and the first reference voltage, and
the reference voltage selection circuit selects the second reference voltage as well as the first reference voltage based on the second control signal, and outputs the first reference voltage and second reference voltage selected.
3. The PLL circuit according to claim 2 , wherein when the control voltage falls within a voltage range between the first reference voltage and the second reference voltage, the reference voltage selection circuit selects and outputs the first reference voltage and the second reference voltage so as to increase the voltage range.
4. The PLL circuit according to claim 2 , wherein the comparison circuit comprises:
a first comparator that detects the potential difference between the first reference voltage and the control voltage;
a second comparator that detects the potential difference between the second reference voltage and the control voltage; and
a control circuit that outputs the first control signal and the second control signal based on comparison results of the first comparator and the second comparator.
5. The PLL circuit according to claim 1 , wherein
the automatic adjustment circuit further comprises a reference voltage generation circuit that generates a plurality of reference voltages having different potentials, based on a voltage drop of resistor elements connected in series between a high-potential side power supply and a low-potential side power supply, and
the reference voltage selection circuit selects and outputs any of the plurality of reference voltages.
6. The PLL circuit according to claim 2 , wherein
the automatic adjustment circuit further comprises a reference voltage generation circuit that generates a plurality of reference voltages having different potentials, based on a voltage drop of resistor elements connected in series between a high-potential side power supply and a low-potential side power supply, and
the reference voltage selection circuit selects and outputs any of the plurality of reference voltages.
7. The PLL circuit according to claim 1 , further comprising a second frequency dividing circuit that is provided between the frequency dividing circuit and the phase frequency detector, divides a frequency of the feedback signal, and outputs the feedback signal to the phase frequency detector.
8. The PLL circuit according to claim 2 , further comprising a second frequency dividing circuit that is provided between the frequency dividing circuit and the phase frequency detector, divides a frequency of the feedback signal, and outputs the feedback signal to the phase frequency detector.
9. The PLL circuit according to claim 7 , wherein the frequency dividing circuit outputs the feedback signal to the second frequency dividing circuit and also to an outside as an output clock signal.
10. The PLL circuit according to claim 8 , wherein the frequency dividing circuit outputs the feedback signal to the second frequency dividing circuit and also to an outside as an output clock signal.
11. A method of controlling a PLL circuit, comprising:
detecting a phase difference between a reference signal and a feedback signal;
generating a control voltage based on the phase difference;
controlling a frequency of a clock signal output based on the control voltage;
controlling a frequency division ratio of the clock signal based on a potential difference between the control voltage and a first reference voltage, to generate the feedback signal; and
controlling the first reference voltage based on the potential difference between the control voltage and the first reference voltage.
12. The method of controlling a PLL circuit according to claim 11 , wherein
the feedback signal is generated by controlling the frequency division ratio of the clock signal based on a potential difference between the control voltage and a second reference voltage as well as on the potential difference between the control voltage and the first reference voltage, and
the first reference voltage and the second reference voltage are controlled based on the potential difference between the control voltage and the second reference voltage as well as on the potential difference between the control voltage and the first reference voltage.
13. The method of controlling a PLL circuit according to claim 12 , wherein when the control voltage falls within a voltage range between the first reference voltage and the second reference voltage, the first reference voltage and the second reference voltage are controlled so as to increase the voltage range between the first reference voltage and the second reference voltage.