Processor, multiprocessor, and debugging method
A processor, a multiprocessor, and a debugging method for solving the conventional problems, one of which is very difficult to switch among debug programs and start the selected program within a certain time. The above convention problem can be solved by a processor that includes a debug unit block, a multimode debug interrupt control block, and an execution block. The debug unit block monitors the execution of the debug target user program and issues a debug interrupt when a predetermined debug condition is satisfied. The control block, upon receiving such a debug interrupt, specifies a debug mode that selects a predetermined debug program. When the debug unit block issues such a debug interrupt, the execution block selects and executes a debug program according to the debug mode specified by the control block.
1 . A processor comprising:
a debug unit block that monitors an execution of a debug target user program and issues a debug interrupt when a debug condition is satisfied;
a multimode debug interrupt control block that specifies a debug mode for selecting a predetermined debug program upon receiving the debug interrupt; and
an execution block that selects a debug program and executes the debug program according to the debug mode specified by the multimode debug interrupt control block when the debug unit block issues the debug interrupt.
2 . The processor according to claim 1 ,
wherein the execution block includes an address selection block that selects a first address for accessing a first debug program or a second address for accessing a second debug program according to the debug mode, and
wherein the execution block fetches an instruction from the address selected by the address selection block and executes the instruction.
3 . The processor according to claim 2 ,
wherein the multimode debug interrupt control block includes a register that stores data used to set the correspondence between the debug interrupt and the predetermined debug program; and
wherein the control block, upon receiving the debug interrupt, refers to the register to specify a debug mode.
4 . The processor according to claim 3 ,
wherein the debug unit block issues the first type debug interrupt when the first type debug condition is satisfied and the second type debug interrupt when the second type debug condition is satisfied, and
wherein the register of the multimode debug interrupt control block stores first data that relates the first type debug interrupt to the first debug program and second data that relates the second type debug interrupt to the second debug program.
5 . The processor according to claim 4 ,
wherein the debug unit block, upon receiving the first type debug condition set by a user operation, issues a first type debug interrupt by assuming a debug condition to be satisfied in relation to the specific processing as the first type debug condition.
6 . The processor according to claim 5 ,
wherein the execution block, if a debug mode is specified so as to select the second debug program and there is no certain time limit for switching to the second debug program, waits until a second type debug interrupt is issued and the second debug program is loaded, then executes the second debug program.
7 . A multiprocessor system comprising:
A first and second processor, each of processors comprising:
a debug unit block that monitors an execution of a debug object program and issues a debug interrupt when a debug condition is satisfied;
a multimode debug interrupt control block that specifies a debug mode for selecting a predetermined debug program upon receiving the debug interrupt; and
an execution block that selects a debug program and executes the debug program according to the debug mode specified by the multimode debug interrupt control block when the debug unit block issues the debug interrupt,
wherein the multimode debug interrupt control block in the first processor, when a debug interrupt is issued in the first processor, specifies the same debug mode as that set in the first processor for the multimode debug interrupt control block in the second processor and sends a simultaneous break interrupt to the control block in the second processor so as to start the simultaneous break debug interrupt; and
wherein the multimode debug interrupt control block in the second processor, when receiving the specification of the same debug mode as that set in the first processor from the multimode debug interrupt control block in the first processor and receiving the simultaneous break interrupt, starts the debug interrupt in the second processor and specifies the same debug mode as that in the first processor for the execution block in the second processor.
8 . The multiprocessor according to claim 7 ,
wherein the second processor includes a masking block that determines whether to enable the simultaneous break interrupt received from the first processor; and
wherein the second processor, when the masking block enables the simultaneous break interrupt, starts the simultaneous break interrupt in the second processor; and
wherein the second processor, when the masking block disables the simultaneous break interrupt, does not start the simultaneous break interrupt in the second processor.
9 . A debugging method to be executed in a processor, comprising:
monitoring the execution of a debug target user program in the processor and starts a debug interrupt when a debug condition is satisfied;
specifying a debug mode used to select a predetermined debug program upon receiving the debug interrupt in the processor; and
selecting and executing the predetermined debug program according to the specified debug mode upon receiving a debug interrupt in the processor.
10 . The debug method according to claim 9 , wherein the executing of the predetermined debug program includes:
selecting a first address for accessing a first debug program or a second address for accessing a second debug program according to the debug mode so as to execute the predetermined debug program; and
fetching an instruction from the selected address.