Semiconductor integrated circuit including transmitter and receiver which conducts loopback test and test method thereof
A semiconductor integrated circuit includes an oscillation circuit for generating multiple clocks of mutually different phases, and is also characterized in selecting a single clock FCLK_P from among multiple clocks FCLK_P [n-1:0] for use in transmitting IQ Serial transmission signals and, utilizing the FCLK_P to transmit an IQ Serial transmission signal.
1 . A semiconductor integrated circuit comprising:
an oscillation circuit for generating multiple clocks with mutually different phases,
wherein a single clock is selected from the multiple clocks for use in sending a transmission signal, and the transmission signal is sent by utilizing the selected single clock.
2 . The semiconductor integrated circuit according to claim 1 , further comprising:
a transmit circuit to send the transmission signal; and
a receive circuit to receive the transmission signal sent from the transmit circuit during a loopback test,
wherein the receive circuit utilizes the multiple clocks to perform a receive processing.
3 . The semiconductor integrated circuit according to claim 2 ,
wherein the transmit circuit includes a parallel-serial converter circuit to convert multiple bits of parallel data to serial data, and
wherein the transmit circuit sends the serial data as the transmission signal.
4 . The semiconductor integrated circuit according to claim 3 , further comprising:
a phase adjuster unit to select a single clock from the multiple clocks,
wherein the transmit circuit includes multiple parallel-serial converter circuits to operate in synchronization with each of the multiple clocks, and
wherein the transmit circuit sends the serial data output from the parallel-serial converter circuit corresponding to the single clock selected by the phase adjuster unit as the transmission signal.
5 . The semiconductor integrated circuit according to claim 3 , further comprising:
a phase adjuster unit to switch the single clock selected from the multiple clocks, to another clock,
wherein the parallel-serial converter circuit synchronizes with the another clock to which the phase adjuster unit switched and performs parallel-serial conversion.
6 . The semiconductor integrated circuit according to claim 2 ,
wherein the transmit circuit sends the transmission signal as frames, and
wherein the receive circuit includes a synchronization detector unit to detect synchronization by receive processing that utilizes multiple clocks for the synchronized information contained in the frame during the loopback test, and also identifies the synch-detected clock as a selected candidate clock.
7 . The semiconductor integrated circuit according to claim 6 ,
wherein the receive circuit further includes a clock handoff unit to receive data signals output by the synchronization detector unit at the multiple clocks, and convey the data signals received to a standard clock.
8 . The semiconductor integrated circuit according to claim 2 ,
wherein a differential circuit connects the transmit circuit and the receive circuit and, during the loopback test, the transmission signals are sent and received by way of the differential circuit.
9 . A test method for a semiconductor integrated circuit including an oscillation circuit to generate multiple clocks of mutually different phases, a transmit circuit to send a transmission signal, and a receive circuit to receive the transmission signal sent by the transmit circuit during a loopback test operation, the method comprising:
selecting a single clock from the multiple clocks for use in sending the transmission signal and, to send the transmission signal by utilizing the selected single clock; and
performing a receive processing by utilizing the multiple clocks.