Low resistivity single crystal silicon carbide wafer
View Patent ↗The invention provides a low resistivity silicon carbide single crystal wafer for fabricating semiconductor devices having excellent characteristics. The low resistivity silicon carbide single crystal wafer has a specific volume resistance of 0.001 Ωcm to 0.012 Ωcm and 90% or greater of the entire wafer surface area is covered by an SiC single crystal surface of a roughness (Ra) of 1.0 nm or less.
1. A low resistivity silicon carbide single crystal wafer having a specific volume resistance of 0.001 Ωcm to 0.012 Ωcm, wherein 90% or greater of the entire wafer surface area over both sides of the wafer has a surface roughness (Ra) of 1.0 nm or less, wherein the basal plane stacking fault density in the wafer after high-temperature annealing at 1000° C. to 1800° C. is 30 cm −1 or less.
2. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein 95% or greater of the entire surface area over both sides of the wafer has a surface roughness (Ra) of 1.0 nm or less.
3. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the specific volume resistance is 0.001 Ωcm to 0.009 Ωcm.
4. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the surface roughness (Ra) is 0.6 nm or less.
5. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the surface roughness (Ra) is 0.3 nm or less.
6. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the crystal polytype of the SiC single crystal wafer is 4H.
7. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the thickness of the SiC single crystal wafer is 0.05 mm to 0.4 mm.
8. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the thickness of the SiC single crystal wafer is 0.05 mm to 0.25 mm.
9. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein an offset angle of the SiC single crystal wafer from an {0001} face is 1° to 12°.
10. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the diameter of the wafer is 50 mm to 300 mm.
11. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the basal plane stacking fault density in the wafer after high-temperature annealing in the case of high-temperature annealing at 1000° C. to 1800° C. is 10 cm −1 or less.
12. An SiC epitaxial wafer comprising an SiC film epitaxially grown on a low resistivity silicon carbide single crystal wafer according to claim 1 .
13. An epitaxial wafer comprising a film of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or a mixed crystal thereof epitaxially grown on a low resistivity silicon carbide single crystal wafer according to claim 1 .
14. A low resistivity silicon carbide single crystal wafer according to claim 1 , wherein the surface roughness (Ra) is measured in a 10 μm square region on the wafer surface.