Semiconductor device
View Patent ↗The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
1. A semiconductor device comprising a request interface circuit and a response interface circuit, wherein
the request interface circuit has a plurality of request queues,
the response interface circuit has a plurality of response queues, and
the request interface circuit receives a request including (i) a queue reservation instruction for reserving one or more request queues from among the plurality of request queues and one or more response queues from among the plurality of response queues and (ii) a number of queues to be reserved, wherein
the semiconductor device includes a plurality of serially connected memory devices, and
each of the plurality of memory devices (i) includes the request interface circuit and the response interface circuit, (ii) has a respective plurality of request queues for transmitting and receiving requests and a respective plurality of response queues for transmitting and receiving responses, (iii) receives the request, (iv) has an ID register for storing an ID number of the memory devices, and (v) has a comparison circuit for comparing a value of the request to the ID number of the memory devices.
2. The semiconductor device as claimed in claim 1 , wherein the response interface circuit transmits reservation completion information indicating that the queue reservation instruction has been successfully processed, after completing reservation of the one or more request queues and the one or more response queues in response to the queue reservation instruction.
3. The semiconductor device as claimed in claim 1 , wherein the semiconductor device includes a memory control circuit.
4. The semiconductor device as claimed in claim 1 , wherein the semiconductor device includes an information processing circuit.
5. The semiconductor device as claimed in claim 1 , wherein the semiconductor device includes a memory device.
6. The semiconductor device as claimed in claim 1 , wherein each of the plurality of memory devices transmits reservation completion information indicating that the queue reservation instruction has been successfully processed, after completing reservation of the one or more request queues and the one or more response queues in response to the queue reservation instruction.
7. The semiconductor device as claimed in claim 1 , wherein
the plurality of memory devices include a first memory device and a second memory device connected to a subsequent stage of the first memory device, and
the first memory device transmits, if the comparison circuit of the first memory device determines that the value of the request does not match the ID number of the first memory device stored in the ID register of the first memory device, the queue reservation instruction received by the first memory device to the second memory device.
8. The semiconductor device as claimed in claim 6 , wherein
the plurality of memory devices include a first memory device and a second memory device connected to a subsequent stage of the first memory device, and
the second memory device transmits the reservation completion information to the first memory device.
9. The semiconductor device of claim 6 , wherein if the comparison circuit of the first memory device determines that the value of the request does not match the ID number of the first memory device stored in the ID register of the first memory device, the first memory device reserves, based on the received request, one or more of its respective plurality of request queues and one or more of its respective plurality of response queues for communication with the second memory device.