IP Library Granted Patent US 8,236,622
Granted Patent B2
US 8,236,622 · App. 12/603,936 · Granted Aug 7, 2012

Method for cutting electric fuse

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Quick Facts
Patent No.
US 8,236,622
App. No.
12/603,936
Granted
Aug 7, 2012
Kind
B2
Abstract

A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Claims (5)

1. A method for cutting an electric fuse, said electric fuse including a first interconnect, a via coupled to said first interconnect, and a second interconnect coupled to said via, wherein said first interconnect, said via, and said second interconnect are formed in different layers on a semiconductor substrate, and wherein an electric conductor constitutes said interconnects and said via;

applying a predetermined electric voltage between said first interconnect and said second interconnect;

flowing the electric conductor in a direction toward and into an insulating film adjacent a periphery of said second interconnect and from an area where said first interconnect and the via are adjacent in which a void region will be formed; and

forming the void region between the via and the first interconnect, or in the via.

2. The method for cutting an electric fuse as set forth in claim 1 , wherein in said applying the predetermined electric voltage between said first interconnect and said second interconnect, a portion said electric conductor, the portion constituting said second interconnect, flows in the direction toward and into the insulating film adjacent the periphery of said second interconnect and from the void region to have said via migrate toward a direction to said second interconnect from said via to form said void region.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025193/0138 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2009
From: UEDA, TAKEHIRO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 023410/0478 →