Granted Patent B1

US 7,843,218 · App. 12/607,657 · Granted Nov 30, 2010

Abstract

Claims (37)

1. A data storage circuit, comprising:

a multiplexer for receiving functional data and scan data inputs and generating a multiplexer output signal under control of a scan enable signal;

a master latch for generating a master latch output signal from said multiplexer output signal at a hold time under control of a master clock signal;

a slave latch for generating a flip flop output signal from said master latch output signal at a launch time under control of a slave clock signal;

clock generation circuitry for receiving a first clock signal and generating therefrom a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode; and

data propagation logic circuitry operable to use said first and second clock signals to generate the master and slave clock signals during a scan mode to delay data launch at the slave latch with respect to data capture at the master latch, and to generate the master and slave clock signals during a functional mode so that data launch at the slave latch coincides with data capture at the master latch.

2. The data storage circuit of claim 1 , where the data propagation logic circuitry generates master and slave clock signals which provide the flip-flop circuit with multiplexed data flip-flop behavior during the functional mode and with level-sensitive scan design behavior during the scan mode.

3. The data storage circuit of claim 1 , where the clock generation circuitry generates the second clock signal during the scan mode as an inverted version of the first clock signal but having signal transitions in a first direction that are time shifted by a predetermined time interval from signal transitions in a second opposite direction at the first clock signal.

4. The data storage circuit of claim 1 , where the data propagation logic circuitry applies an inverted version of the first clock signal to the slave latch during the functional mode and applies the second clock signal to clock the slave latch during the scan mode so as to delay data launch at the slave latch with respect to data capture at the master latch.

5. The data storage circuit of claim 1 , where the clock generation circuitry comprises:

a delay element coupled to generate a delayed clock signal from the first clock signal;

a NOR gate coupled to receive the first clock signal and the delayed clock signal and to generate therefrom a NOR output signal;

an OR gate coupled to receive the NOR output signal and an inverted version of the scan enable signal and to generate therefrom the second clock signal.

6. The data storage circuit of claim 1 , where the clock generation circuitry comprises:

a delay element coupled to generate a delayed clock signal from the first clock signal; and

an OR gate coupled to receive the delayed clock signal and an inverted version of the scan enable signal and to generate therefrom the second clock signal.

7. The data storage circuit of claim 6 , where the data propagation logic circuitry comprises a NAND gate coupled to receive the first and second clock signals and to generate therefrom the slave clock signal.

8. The data storage circuit of claim 1 , where the clock generation circuitry generates the second clock signal during the scan mode to be time-shifted by a predetermined time interval with respect to said first clock signal.

9. The data storage circuit of claim 1 , where the data propagation logic circuitry applies an inverted version of the first clock signal to the master latch during the functional mode and applies the second clock signal to clock the master latch during the scan mode so as to advance data capture at the master latch with respect to data launch at the slave latch.

10. The data storage circuit of claim 9 , where the data propagation logic circuitry applies an inverted version of the first clock signal to the slave latch during the scan mode so as to advance data capture at the master latch with respect to data launch at the slave latch.

11. The data storage circuit of claim 8 , where the clock generation circuitry comprises:

a delay element coupled to generate a delayed clock signal from the first clock signal; and

a NOR gate coupled to receive the delayed clock signal and an inverted version of the scan enable signal, and to generate therefrom the second clock signal.

12. The data storage circuit of claim 11 , where the data propagation logic circuitry comprises a NOR gate coupled to receive the first and second clock signals and to generate therefrom the master clock signal.

13. The data storage circuit of claim 1 , where the multiplexer, master latch, slave latch, and data propagation logic circuitry comprise a flip-flop circuit.

14. The data storage circuit of claim 1 , where the multiplexer, master latch, slave latch, clock generation circuitry, and data propagation logic circuitry comprise a flip-flop circuit.

15. A method for operating a master latch which is connected in series with a slave latch using a single input clock to provide multiplexed data flip flop (MUX DFF) behavior during a functional mode and level sensitive scan design (LSSD) behavior during a scan mode, comprising:

applying, during the functional mode, the single input clock and an inverted version of the single input clock to clock the master and slave latches; and

applying, during the scan mode, the single input clock and a second clock generated from the single input clock to generate master and slave clocks for clocking the master and slave latches, whereby the slave clock has a non-overlapping periodic signal transition edge in a first direction that is delayed with respect to a periodic signal transition edge in a second opposite direction of the master clock.

16. The method of claim 15 , where applying, during the scan mode, the single input clock and the second clock comprises applying the single input clock to clock the master latch and applying the second clock to clock the slave latch so that the second clock has a periodic rising edge that is delayed with respect to a periodic falling edge of the single input clock.

17. The method of claim 15 , where applying, during the scan mode, the single input clock and the second clock comprises applying the single input clock to clock the slave latch and applying the second clock to clock the master latch so that the single input clock has a periodic rising edge that is delayed with respect to a periodic falling edge of the second clock.

18. The method of claim 15 , where the master and slave clocks are applied to clock the master and slave latches during the scan mode so that the slave latch launch is delayed with respect to the master latch closing.

19. A system for propagating data in a datapath, comprising:

a plurality of clocked data storage elements arranged in a datapath and operable to receive input functional data or scan data under control of a scan enable signal and to generate output data therefrom;

a clock generator which receives a first clock signal and generates therefrom a non-overlapping second clock signal as a steady state signal during a functional mode and as a switching clock signal during a scan mode, where the switching clock signal during the scan mode has signal transitions in a first direction that are time shifted by a predetermined time interval from signal transitions in a second opposite direction at the first clock signal; and

data propagation logic circuitry operable to use said first clock signal to cause functional data to propagate through said clocked data storage elements during a functional mode, and operable to use the first clock signal and the non-overlapping second clock signal to cause scan data to propagate through said clocked data storage elements during a scan mode to inhibit hold time violations from occurring at the clocked data storage elements.

20. A system of claim 19 , wherein said plurality of clocked data storage elements are configured as edge-triggered multiplexed data flip-flop latches.

Assignments (15)