Semiconductor device and manufacturing method thereof
View Patent ↗To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.
1. A semiconductor device comprising:
a first level wiring structure formed over a substrate, the first level wiring structure including first and second wiring patterns disposed with a first gap therebetween, two or more first dummy patterns arranged in the first gap between the first and second wiring patterns and a first insulating layer covering the first and second wiring patterns and the first dummy patterns; and
a second level wiring structure formed on the first level wiring structure, the second level wiring structure including third and fourth wiring patterns disposed with a second gap therebetween that is less than the first gap, one or more second dummy patterns arranged in the second gap between the third and fourth wiring patterns and a second insulating layer covering the third and fourth wiring patterns and second dummy patterns; the second dummy patterns being smaller in number than the first dummy patterns and each second dummy pattern being vertically aligned in central axis with an associated one of the first dummy patterns.
2. The device as claimed in claim 1 , wherein each of the first and second dummy patterns are formed in substantially the same size so that a distance between one of the first and second wiring patterns and an adjacent one of the first dummy patterns thereto is smaller than a distance between one of the third and fourth wiring patterns and an adjacent one of the second dummy patterns thereto.
3. The device as claimed in claim 1 , wherein at least one of the second dummy patterns is smaller in size than a corresponding one of the first dummy patterns.
4. The device as claimed in claim 1 , wherein at least one of the second dummy patterns is larger in size than a corresponding one of the first dummy patterns.
5. The device as claimed in claim 1 , further comprising a third level wiring structure formed on the second level wiring structure, the third level wiring structure including fifth and sixth wiring patterns disposed with a third gap therebetween that is less than the second gap, one or more third dummy patterns arranged in the third gap between the fifth and sixth wiring patterns and a third insulating layer covering the fifth and sixth wiring patterns and the third dummy patterns, each third dummy pattern being vertically aligned in central axis with a corresponding second dummy pattern.
6. The device as claimed in claim 5 , wherein the third dummy patterns is equal in number to the second dummy patterns, and each of the first, second and third dummy patterns are formed in substantially the same size, a distance between one of the first and second wiring patterns and an adjacent one of the first dummy patterns thereto being smaller than a distance between one of the third and fourth wiring patterns and an adjacent one of the second dummy patterns thereto.
7. The device as claimed in claim 5 , wherein the third dummy patterns is equal in number to the second dummy patterns, and each third dummy pattern is smaller in size than a corresponding second dummy pattern.
8. The device as claimed in claim 7 , wherein at least one of the second dummy patterns is larger in size than a corresponding one of the first dummy patterns.
9. The device as claimed in claim 5 , wherein the third dummy patterns is smaller in number than the second dummy patterns.
10. The device as claimed in claim 9 , wherein the third dummy pattern is larger in size than a corresponding second dummy pattern.
11. A semiconductor device comprising:
a first level wiring structure formed over a semiconductor substrate, the first level wiring structure comprising a plurality of first-level wiring patterns that include first and second wiring patterns that are adjacent to each other without intervention of any other first-level wiring patterns, at least two first dummy patterns disposed in a first space between the first and second wiring patterns, and a first insulating layer covering the first and second wiring patterns and the first dummy patterns; and
a second level wiring structure formed over the first level wiring structure, the second level wiring structure comprising a plurality of second-level wiring patterns that include third and fourth wiring patterns adjacent to each other without intervention of any other second-level wiring patterns, at least one second dummy pattern arranged in a second space between the third and fourth wiring patterns, and a second insulating layer covering the third and fourth wiring patterns and second dummy patterns;
the second space being less than the first space, the second dummy pattern being smaller in number than the first dummy patterns, and the second dummy pattern being vertically aligned in central axis with a corresponding one of the first dummy patterns.
12. The device as claimed in claim 11 , wherein the number of the first dummy patterns is three or more and the number of the second dummy patterns is two or more, the second dummy patterns being vertically aligned in central axis with corresponding ones of the first dummy patterns, respectively.
13. The device as claimed in claim 11 , further comprising:
a third level wiring structure formed over the second level wiring structure, the third level wiring structure comprising a plurality of third-level wiring patterns that include fifth and sixth wiring patterns adjacent to each other without intervention of any other third-level wiring patterns, at least one third dummy pattern arranged in a third space between the fifth and sixth wiring patterns, and a third insulating layer covering the fifth and sixth wiring patterns and third dummy patterns;
the third space being less than the first space, the third dummy pattern being smaller in number than the first dummy patterns, and the third dummy pattern being vertically aligned in central axis with the second dummy pattern.
14. The device as claimed in claim 13 , wherein the number of the first dummy patterns is three or more, the number of the second dummy patterns is two or more, and the number of the third dummy patterns is two or more, the second dummy patterns being vertically aligned in central axis with corresponding ones of the first dummy patterns, respectively, and the third dummy patterns being vertically aligned in central axis with corresponding ones of the second dummy patterns, respectively.