Granted Patent B2

US 8,324,878 · App. 12/610,959 · Granted Dec 4, 2012

Abstract

Claims (33)

1. A voltage regulator comprising:

an active control switch coupled between an input voltage line and an input of an energy storage device;

an active sync switch coupled to the input of the energy storage device;

a driver circuit coupled to the control and sync switches, the driver circuit to alternately drive each of the control and sync switches into a conducting state to produce a regulated voltage at an output of the energy storage device; and

a gate resistor coupled in series within a control path of the sync switch, wherein the gate resistor has a resistance value that is tuned to reduce an anticipated dead time between a turn-off time of the sync switch and a turn-on time of the control switch.

2. The voltage regulator of claim 1 , wherein the resistance value of the gate resistor is further tuned to reduce an anticipated voltage spike event during a turn-on time of the control switch.

3. The voltage regulator of claim 1 , wherein the control and sync switches comprise metal-oxide semiconductor field effect transistor (MOSFET) switches.

4. The voltage regulator of claim 3 , wherein the resistance value of the gate resistor is further tuned to delay the turn-off time and extend a conduction time of the sync MOSFET switch.

5. The voltage regulator of claim 4 , wherein the anticipated dead time between the turn-off time of the sync switch and the turn-on time of the active switch comprises a default dead time of the driver circuit, and the resistance value of the gate resistor is further tuned to implement an effective dead time that is less than the default dead time of the driver circuit.

6. The voltage regulator of claim 3 , wherein the resistance value of the gate resistor is further tuned to reduce a time during which current flows through a body diode of the sync MOSFET switch.

7. The voltage regulator of claim 1 , wherein the gate resistor is located in a control line between an output of the driver circuit and a gate input of the sync switch.

8. The voltage regulator of claim 1 , wherein the driver circuit comprises an integrated circuit, and the gate resistor is located within the integrated circuit.

9. The voltage regulator of claim 8 , wherein the gate resistor is implemented within the driver circuit as an increased output impedance in the control path of the sync switch.

10. The voltage regulator of claim 9 , wherein the output impedance in the control path of the sync switch is variable, and the driver circuit is configured to dynamically change the output impedance for different operating modes.

11. The voltage regulator of claim 1 , wherein the sync switch comprises a MOSFET device with a gate, and the gate resistor is integrated within the MOSFET device and coupled in series with the gate.

12. The voltage regulator of claim 11 , wherein the gate resistor is implemented within the MOSFET device as an increased internal gate resistance in the control path of the sync switch.

13. A method for operating a voltage regulator, the method comprising:

driving an active sync switch in a conducting state within a switching-mode voltage regulator;

controlling a gate control path of the active sync switch to stop driving the active sync switch at a beginning of a default dead time of a driver circuit coupled to the control path of the active sync switch;

extending a time of the conducting state of the active sync switch during the default dead time of the driver circuit via a gate resistance within the control path of the active sync switch, wherein the gate resistance has a resistance value tuned for the combined operating parameters of the active sync switch and the driver circuit; and

driving an active control switch in a conducting state at an end of the default dead time of the driver circuit.

14. The method of claim 13 , wherein the resistance value of the gate resistance is further tuned to reduce an anticipated voltage spike event during a turn-on time of the control switch.

15. The method of claim 13 , wherein the gate resistance is implemented in a discrete gate resistor between a sync switch driver output of the driver circuit and a gate of the active sync switch.

16. The method of claim 13 , wherein the gate resistance is implemented within an output impedance of a sync switch driver output of the driver circuit, wherein the sync switch driver output of the driver circuit is coupled to a gate of the active sync switch.

17. The method of claim 13 , wherein the gate resistance is implemented within an internal gate resistance of the active sync switch, wherein the active sync switch comprises a sync MOSFET switch.

18. A sync MOSFET switch for a voltage regulator, the sync MOSFET switch comprising:

a source node coupled to reference potential;

a drain node coupled to a source node of a corresponding control MOSFET switch and also coupled to an input of an energy storage device, wherein the control and sync MOSFET switches are configured to produce a regulated voltage at an output of the energy storage device; and

a gate node coupled to a gate driver integrated circuit (IC) via a gate control path, wherein the gate control path comprises a gate resistance that is tuned to reduce:

an anticipated dead time between a turn-off time of the sync MOSFET switch and a turn-on time of the control MOSFET switch; and

an anticipated voltage spike event during a turn-on time of the control MOSFET switch.

19. The sync MOSFET switch of claim 18 , wherein the tuned gate resistance is at least partially integrated within an internal gate resistance of the gate node of the sync MOSFET switch.

20. The sync MOSFET switch of claim 18 , wherein the gate node is coupled to a discrete gate resistor having the tuned gate resistance, wherein the discrete gate resistor is coupled within the gate control path.

Assignments (12)