IP Library Granted Patent US 8,187,929
Granted Patent B2
US 8,187,929 · App. 12/612,123 · Granted May 29, 2012

Mask level reduction for MOSFET

Assignee: CBRITE, Inc.
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Quick Facts
Patent No.
US 8,187,929
App. No.
12/612,123
Granted
May 29, 2012
Kind
B2
Abstract

A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer.

Claims (32)

1. A method of fabricating a thin film transistor and transparent light transmission area for an active matrix display with reduced masking operations, the method comprising the steps of:

providing a transparent substrate with a surface;

patterning gate metal on the surface of the substrate to define a thin film transistor gate;

forming a layer of transparent gate dielectric over the gate and surrounding substrate surface;

depositing a layer of transparent semiconducting metal oxide on the layer of gate dielectric;

patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;

depositing at least a source/drain metal layer on the channel protection layer and the exposed semiconducting metal oxide;

in a single etching step, etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals and etching through the source/drain metal layer and the semiconducting metal oxide at the periphery to isolate the thin film transistor;

patterning a nonconductive spacer layer on the isolated thin film transistor and portions of the surrounding source/drain metal layer, the spacer layer defining a light transmission area adjacent the channel area designed to receive a light transmitting device in overlying relationship; and

using the patterned nonconductive layer as a mask etching through the source/drain metal layer in the light transmission area to expose the semiconducting metal oxide as a transparent pixel terminal contacting or forming one terminal of the overlying light transmitting device.

2. A method as claimed in claim 1 wherein the fabrication of the thin film transistor includes fabricating a plurality of thin film transistors in an active matrix display, the active matrix display including a matrix of data lines and scan lines with the gate metal being connected to one of the scan lines and the source/drain metal being connected to one of the data lines.

3. A method as claimed in claim 1 wherein the light transmitting device includes one of a liquid crystal device (LCD) and an organic light emission device (OLED).

4. A method as claimed in claim 1 wherein the spacer layer is positioned to separate the substrate and associated components formed thereon from adjacent substrate formations in the active matrix display.

5. A method as claimed in claim 1 wherein the step of depositing at least a source/drain metal layer includes depositing a layer of transparent oxide on the channel protection layer and the exposed semiconducting metal oxide prior to depositing the source/drain metal layer.

6. A method as claimed in claim 5 wherein the step of depositing at least a source/drain metal layer includes depositing a barrier metal layer on the layer of transparent oxide.

7. A method as claimed in claim 6 wherein the step of depositing the barrier metal layer includes depositing one of Mo, W, Cr, and Ni.

8. A method of fabricating a matrix of thin film transistors in an active matrix display, the active matrix display including a matrix of data lines and scan lines, the method comprising the steps of:

providing a transparent substrate with a surface;

patterning gate metal on the surface of the substrate to define a gate for each thin film transistor of the matrix, and connecting the gate of each thin film transistor of the matrix to a selected scan line;

forming a layer of transparent gate dielectric over each of the gates and surrounding substrate surface;

depositing a layer of transparent semiconducting metal oxide on the layer of gate dielectric;

patterning a channel protection layer on the semiconducting metal oxide overlying each gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above each gate and to expose the remaining semiconducting metal oxide;

depositing at least a source/drain metal layer on the channel protection layer and the exposed semiconducting metal oxide;

in a single etching step, etching through the source/drain metal layer to the channel protection layer above each gate to separate the source/drain metal layer into thin film transistor source and drain terminals and etching through the source/drain metal layer and the semiconducting metal oxide at the periphery to isolate each thin film transistor of the matrix, and connecting each of the source/drain terminals to one of the data lines;

patterning a nonconductive spacer layer on the isolated thin film transistor and portions of the surrounding source/drain metal layer, the spacer layer defining a light transmission area adjacent the channel area designed to receive a light transmitting device in overlying relationship; and

using the patterned nonconductive layer as a mask etching through the source/drain metal layer in the light transmission area to expose the semiconducting metal oxide as a transparent pixel terminal.

9. A method as claimed in claim 8 wherein the transparent pixel terminal in the light transmission area is an electrode of a light emission device in the active matrix display.

10. A method as claimed in claim 9 wherein the light emission device includes one of a liquid crystal emission device (LCD) and an organic light emission device (OLED).

11. A method as claimed in claim 9 wherein the spacer layer is positioned to separate the substrate and associated components formed thereon from adjacent substrate formations in the active matrix display.

12. A method as claimed in claim 8 wherein the step of depositing at least a source/drain metal layer includes depositing a layer of transparent oxide on the channel protection layer and the exposed semiconducting metal oxide prior to depositing the source/drain metal layer.

13. A method as claimed in claim 12 wherein the step of depositing at least a source/drain metal layer includes depositing a barrier metal layer on the layer of transparent oxide.

14. A method as claimed in claim 13 wherein the step of depositing the barrier metal layer includes depositing one of Mo, W, Cr, and Ni.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED ON REEL 048069 FRAME 0427. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Apr 13, 2020
From: FULL STRENGTH GROUP LIMITED
To: ABC SERVICES GROUP, INC., SOLELY IN ITS CAPACITY AS ASSIGNEE FOR THE BENEFIT OF CREDITORS OF CBRITE INC.; CBRITE INC.
Reel/Frame 052384/0832 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED AT REEL: 045653 FRAME: 0823. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 13, 2020
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 052377/0853 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED AT REEL: 045653 FRAME: 0983. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 13, 2020
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 052377/0913 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED ON REEL 049879 FRAME 0645. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded Apr 13, 2020
From: ABC SERVICES GROUP, INC.
To: FANTASY SHINE LIMITED
Reel/Frame 052384/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2019
From: ABC SERVICES GROUP, INC.
To: FANTASY SHINE LIMITED
Reel/Frame 049879/0645 →
RELEASE OF SECURITY INTEREST Recorded Jan 14, 2019
From: FULL STRENGTH GROUP LIMITED
To: ABC SERVICES GROUP, INC., SOLELY IN ITS CAPACITY AS ASSIGNEE FOR THE BENEFIT OF CREDITORS OF CBRITE INC.; CBRITE INC.
Reel/Frame 048069/0427 →
SECURITY INTEREST Recorded Mar 20, 2018
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 045653/0823 →
SECURITY INTEREST Recorded Mar 20, 2018
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 045653/0983 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2011
From: SHIEH, CHAN-LONG; FOONG, FATT; YU, GANG
To: CBRITE INC.
Reel/Frame 025924/0888 →
Continuity (1)
Related Publication 20110104841A1 · May 5, 2011