Transparent multiplexing of analog-to-digital converters

1. A method comprising:

in response to a first event:

transmitting a first value from a first input of a multiplexer to a first analog-to-digital converter (ADC) of a plurality of ADCs, wherein the first value is transmitted to only one ADC; and

in response to a second event:

transmitting a second value from the first input of the multiplexer to a second ADC of the plurality of ADCs, wherein the second value is transmitted to only one ADC.

2. The method of claim 1 , further comprising:

in response to a third event:

transmitting a third value from the first input of the multiplexer to the first ADC of the plurality of ADCs.

3. The method of claim 1 , further comprising:

reading a flag, wherein

the flag indicates whether a conversion request is pending;

if the flag indicates a conversion request is pending,

adding a first conversion request to a queue and

clearing the flag.

4. The method of claim 3 , wherein the first conversion request identifies:

a pin; and

a priority associated with the pin.

5. The method of claim 1 , further comprising:

accessing a first conversion request.

6. The method of claim 1 , further comprising:

detecting the first ADC's utilization; and

detecting the second ADC's utilization.

7. The method of claim 1 , further comprising:

reading a flag, wherein

the flag indicates whether a sample window is open.

8. The method of claim 1 , further comprising:

receiving a first control signal, wherein

the first control signal specifies the first input to the multiplexer, and

the first control signal specifies an output, wherein the output corresponds to the first ADC of the plurality of ADCs.

9. The method of claim 1 , further comprising:

including an additional ADC in the plurality of ADCs.

10. The method of claim 9 , further comprising:

transmitting a third value from the first input of the multiplexer to the additional ADC.

11. An apparatus comprising:

a multiplexer; and

a control circuit, wherein the control circuit is configured to

initiate transmission of a first value from a first input of the multiplexer to a first analog-to-digital converter (ADC) of a plurality of ADCs, in response to a first event, wherein the transmission of the first value is to only one ADC, and

initiate transmission of a second value from the first input of the multiplexer to a second ADC of the plurality of ADCs in response to a second event, wherein the transmission of the second value is to only one ADC.

12. The apparatus of claim 11 , wherein the control circuit is further configured to

initiate transmission of a third value from the first input of the multiplexer to the first ADC of the plurality of ADCs.

13. The apparatus of claim 11 , further comprising:

a memory, wherein

the memory is configured to store a flag,

the flag is configured to indicate whether a conversion request is pending,

the control circuit is configured to access the memory and determine whether the flag indicates a conversion request is pending;

a queue configured to store at least one conversion request, wherein

the control circuit is configured to add a first conversion request to the queue in response to determining that the flag indicates a conversion request is pending.

14. The apparatus of claim 13 , wherein the first conversion request identifies:

a pin; and

a priority associated with the pin.

15. The apparatus of claim 11 , wherein

the control circuit is further configured to access a first conversion request.

16. The apparatus of claim 11 , wherein the control circuit is further configured to:

detect the first ADC's utilization; and

detect the second ADC's utilization.

17. The apparatus of claim 11 , wherein the control circuit is further configured to:

read a flag, wherein

the flag is configured to indicate whether a sample window is open.

18. The apparatus of claim 11 , wherein the control circuit is further configured to:

specify the first input to the multiplexer, and

specify an output, wherein the output corresponds to the first ADC of the plurality of ADCs.

19. The apparatus of claim 11 , wherein the control circuit is further configured to:

detect an inclusion of an additional ADC in the plurality of ADCs.

20. The apparatus of claim 19 , wherein the control circuit is further configured to:

initiate transmission of a third value from the first input of the multiplexer to the additional ADC.

21. A system comprising:

a means for transmitting a first value from a first input of a multiplexer to a first analog-to-digital converter (ADC) of a plurality of ADCs in response to a first event, wherein the first value is transmitted to only one ADC; and

a means for transmitting a second value from the first input of the multiplexer to a second ADC of the plurality of ADCs in response to a second event, wherein the second value is transmitted to only one ADC.