Efficient decoding
View Patent ↗A decoder includes circuitry for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.
1. A decoder comprising:
means for generating bits representing received signals, and beliefs representing a channel reliability of each bit;
a bit node computation block receiving the bits, associated channel reliability and check node messages, and generating a plurality of bit node messages and beliefs for each bit;
a plurality of M serially-connected pipeline stages for receiving the bit node messages and after M decoding cycles, generating a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different than component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.
2. The decoder of claim 1 , wherein each of the M serially-connected pipeline stages are clocked by a decoding cycle clock.
3. The decoder of claim 1 , further comprising:
every decoding cycle after M decoding cycles, the bit node computation block updating beliefs of the received bits using check node messages of a single one of the component codes per decoding cycle, wherein the single one component of the component codes changes for each decoding cycle according to a specific order of the component codes.
4. The decoder of claim 1 , further comprising:
every decoding cycle, updating all bit node messages of the received bits using check node to bit node messages of a single one of the component codes per decoding cycle, wherein the single one component of the component codes changes for each decoding cycle according to a specific order of the component codes.
5. The decoder of claim 1 , further comprising the bit node computation block generating a decoded received bit stream once every N iterations, wherein N is a pre-selected number of iterations.
6. The decoder of claim 5 , wherein N is dynamically selected depending on whether all parity checks of the component codes are satisfied.
7. The decoder of claim 1 , wherein the check node computations of each of the M serially-connected pipeline stages includes different functionality than all other of the M serially connected pipeline stages.
8. The decoder of claim 1 , wherein for each cycle of decoding, each of M−1 of the M serially-connected pipeline stage executing one step of check node computations and providing intermediate results to a next stage of the M serially-connected pipeline stages.
9. The decoder of claim 1 , wherein for each iteration, each stage of the M serially-connected pipeline stages of decoding using updated bit node messages including all previous iterations.
10. The decoder of claim 1 , further comprising configuring a first of the M serially-connected pipeline stages with a specific component codes, and configuring a last of the M serially-connected pipeline stages with another specific component code.
11. The decoder of claim 10 , further comprising:
a first sub-block of the first stage re-ordering bit node to check node messages, enabling processing of the a second sub-block of the first stage to remain static as the first stage cycles through processing using the J component codes.
12. The decoder of claim 11 , wherein the re-ordering of the bit node to check node messages changes every decoding cycle.
13. The decoder of claim 1 , wherein column weights of a parity check matrix of the component codes are non-zero.
14. The decoder of claim 1 , wherein each component code comprises a regular LDPC, and column weights of a parity matrix of the component codes are pre-selected values.
15. The decoder of claim 14 , wherein the pre-selected values are all the same.
16. The decoder of claim 15 , wherein hardware implementing the stages includes a repeated structure.
17. The decoder of claim 1 , wherein a parity check matrix of the component codes has column weights of one.