IP Library Granted Patent US 7,961,055
Granted Patent B2
US 7,961,055 · App. 12/617,234 · Granted Jun 14, 2011

PLL circuit and oscillator device

Assignee: Fujitsu Semiconductor Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,961,055
App. No.
12/617,234
Granted
Jun 14, 2011
Kind
B2
Abstract

A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Claims (29)

1. A phase locked loop circuit comprising:

an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator; and

a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal,

wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

2. The phase locked loop circuit according to claim 1 ,

wherein the oscillator part comprises

a detecting part configured to divide a preset voltage value into multiple sections and detect a section of the multiple sections in which a voltage value of the control signal is included, and

wherein the drive capability of the oscillator part is controlled in accordance with the section detected by the detecting part.

3. The phase locked loop circuit according to claim 1 ,

wherein the oscillator part comprises

a detecting part configured to divide a preset current value into multiple sections and detect a section of the multiple sections in which a current value of the control signal is included, and

wherein the drive capability of the oscillator part is controlled in accordance with the section detected by the detecting part.

4. The phase locked loop circuit according to claim 1 ,

wherein the drive capability of the oscillator part is controlled after an operation of the oscillator part has become stable.

5. An oscillator device comprising:

a detecting part configured to detect an input to an oscillator part in a phase locked loop circuit;

a drive part configured to connect to an oscillator, drive the oscillator, and output a reference signal to the phase locked loop circuit; and

an adjusting part configured to adjust a drive capability of the drive part on the basis of a detection result from the detecting part.

6. The oscillator device according to claim 5 ,

wherein the adjusting part decreases the drive capability when the input to the oscillator part changes in a direction for increasing a frequency of an output signal of the oscillator part.

7. The oscillator device according to claim 6 ,

wherein the adjusting part includes a resistor part connected in parallel to the oscillator and wherein the adjusting part decreases the drive capability by increasing a resistance value of the resistor part.

8. The oscillator device according to claim 6 ,

wherein the adjusting part includes a buffer connected in parallel to the oscillator and wherein the adjusting part decreases the drive capability by decreasing a drive capability of the buffer.

9. The oscillator device according to claim 5 ,

wherein the detecting part detects the input to the oscillator part on the basis of a plurality of detection values, and

wherein the adjusting part decreases the drive capability stepwise on the basis of detection results corresponding to the plurality of detection values detected by the detecting part.

10. The oscillator device according to claim 5 ,

wherein the input to the oscillator part includes an analog signal based on a phase comparison result in the phase locked loop circuit.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0337 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2009
From: MIYATA, SHINJI; TANAKA, MASAHIRO
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023535/0645 →
Priority Claims (1)
JP 2009-036463 · Feb 19, 2009 · national
Continuity (1)
Related Publication 20100207694A1 · Aug 19, 2010