Structure for integrated circuit alignment
A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
1. A semiconductor wafer comprising:
an exposure field;
a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and
a die alignment mark disposed between the seal ring region and the corner stress relief region without being disposed within any corner stress relief region and any seal ring region,
wherein the die alignment mark is further disposed such that there is no seal ring region between the die alignment mark and the integrated circuit region, and
wherein the corner stress relief region is free of any seal ring region.
2. The wafer of claim 1 further comprising:
a scribe line defining the perimeter of the exposure field; and
an exposure field alignment mark disposed within the scribe line defining the perimeter of the exposure field.
3. The wafer of claim 1 wherein the alignment mark comprises a box-in-box alignment pattern.
4. The wafer of claim 1 wherein the alignment mark includes at least one overlay mark.
5. The wafer of claim 4 wherein the overlay mark is formed in an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.
6. The wafer of claim 1 wherein the die alignment mark comprises a first alignment mark and a second alignment mark.
7. A semiconductor wafer comprising:
an exposure field;
a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and
a die alignment mark disposed between the seal ring region and the corner stress relief region without being disposed within any corner stress relief region and any seal ring region,
wherein the corner stress relief region is free of any seal ring region,
wherein there is not any seal ring region between the die alignment mark and the integrated circuit region, and
wherein the die alignment mark comprises a first alignment mark and a second alignment mark.
8. The wafer of claim 7 further comprising a plurality of layers including an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.
9. The wafer of claim 8 wherein the first alignment mark includes an overlay mark formed in at least one of the OD, POLY, or CO layers.
10. A method comprising:
providing a semiconductor wafer;
defining a field on the semiconductor wafer, wherein a perimeter of the field is defined by a scribe line;
defining a die area within the field, wherein a perimeter of the die is defined by a scribe line;
forming an alignment mark within the scribe line defining the perimeter of the field; and
forming an alignment mark in a corner portion of the die area such that the alignment mark in the corner portion is disposed between a seal ring and a corner stress relief portion and between the seal ring and a circuit region without being disposed within any corner stress relief portion and any seal ring,
wherein there is not any seal ring between the alignment mark in the corner portion and the circuit region,
wherein the corner stress relief portion is free of any seal ring.
11. The method of claim 10 wherein forming the alignment marks comprises utilizing a box-in-box alignment pattern.
12. The method of claim 10 wherein forming the alignment mark in the corner portion of the die area comprises:
forming the seal ring in the die area; and
forming the corner stress relief portion in the die area.
13. The method of claim 10 wherein forming the alignment mark in the corner portion of the die area includes forming an overlay mark in an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.
14. The method of claim 10 further comprising:
performing a pattern recognition technique to align a mask with the alignment marks; and
exposing the semiconductor wafer to form an integrated circuit region.
15. The method of claim 10 , wherein forming the alignment mark in the corner portion of the die area includes forming a first alignment mark and a second alignment mark, wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.
16. The wafer of claim 1 , wherein the die alignment mark includes a first alignment mark and a second alignment mark, wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.
17. The wafer of claim 7 , further comprising:
a scribe line defining the perimeter of the exposure field; and
an exposure field alignment mark disposed within the scribe line defining the perimeter of the exposure field.
18. The wafer of claim 9 , wherein the second alignment mark combination is without an overlay mark formed in at least one of the OD, POLY, or CO layers.
19. The wafer of claim 7 , wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.
20. The wafer of claim 1 , wherein there is no other seal ring region closer to the die than the seal ring region.