Memory device having shifting capability and method thereof
View Patent ↗An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
1. A method, comprising,
receiving first information at a memory array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each of the plurality of rows associated with a corresponding word line and each of the plurality of columns associated with a corresponding bit line;
storing the first information via a first parallel access to a first row of the memory array; and
serially shifting second data information from a first subset of the plurality of bit cells to a second subset of the plurality of bit cells.
2. The method of claim 1 , wherein shifting comprises shifting the second data information along a first row of the memory array.
3. The method of claim 1 , wherein shifting comprises shifting the second data information along a column of the memory array.
4. The method of claim 1 , wherein shifting comprises shifting a first portion of the second data information along a first row of the memory array, and shifting a second portion of the second data information from the first row to a second row of the memory array.
5. The method of claim 1 , wherein shifting comprises shifting a first portion of the second data information along a first column of the memory array, and shifting a second portion of the second data information from the first column to a second column of the memory array.
6. The method of claim 1 , further comprising serially shifting third data information from a third subset of the plurality of bit cells to a fourth subset of the plurality of bit cells and wherein:
shifting the second data information comprises shifting the second data information along a row of the memory array; and
shifting the third data information comprises shifting the third data information along a column of the memory array.
7. The method of claim 1 , further comprising:
receiving a first address;
selecting a first row of the memory array based on the first address and storing third information at the first row via a second parallel access;
receiving a second address;
selecting a second row of the memory array based on the second address and retrieving fourth information from the second row via a third parallel access.
8. A method, comprising:
receiving first information at a memory array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, where each of the plurality of rows is associated with a corresponding word line and each of the plurality of columns is associated with a corresponding bit line;
storing the first information at a first row of the memory array via a parallel access by providing the first information via a plurality of bit lines associated with the first row; and;
shifting second information stored at a first subset of the plurality of bit cells of the memory array to a second subset of the plurality of the bit cells.
9. The method of claim 8 , wherein the first subset of the plurality of bit cells and the second subset of the plurality of bit cells are located on a common row of the memory array.
10. The method of claim 8 , wherein the first subset of the plurality of bit cells and the second subset of the plurality of bit cells are associated with a common column of the memory array.
11. The method of claim 8 , wherein shifting comprises:
in response to a first transition of a clock signal, shifting third data information from a master module of a first bit cell of the first subset of the plurality of bit cells to a slave module of the first bit cell.
12. The method of claim 11 , wherein shifting further comprises:
in response to a second transition of the clock signal, shifting the third data information from the slave module of the first bit cell to a master module of a second bit cell of the first subset of the plurality of bit cells.
13. A memory array, comprising:
a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each of the plurality of rows associated with a corresponding word line and each of the plurality of columns associated with a corresponding bit line, the memory array operable to store information in a parallel manner at a row of the memory array;
each bit cell of at least a subset of the plurality of bit cells configured to receive information from another bit cell of the plurality of bit cells during a shift operation.
14. The memory array of claim 13 , wherein each bit cell of the subset of the plurality of bit cells is configured to receive information from another bit cell on the same row of the memory array during a shift operation.
15. The memory array of claim 14 , wherein each bit cell of the subset of the plurality of bit cells is configured to receive information from an adjacent bit cell of the memory array during a shift operation.
16. The memory array of claim 13 , wherein each bit cell of the subset of the plurality of bit cells is configured to receive information from another bit cell on the same column of the memory array during a shift operation.
17. The memory array of claim 13 , wherein each bit cell of the subset of the plurality of bit cells is configured to selectively receive information from another bit cell on the same row of the memory array or from another bit cell on the same column of the memory array during a shift operation depending on a type of the shift operation.
18. The memory array of claim 13 , wherein one of the subset of the plurality of bit cells comprises:
a first input to receive a clock signal during the first shift operation;
a master latch;
a slave latch coupled to the master latch, the slave latch operable to store data information stored at the master latch in response to a first edge of the clock signal.
19. The memory array of claim 18 , wherein the slave latch is operable to provide data information stored at the slave latch to another bit cell in response to a second edge of the clock signal.
20. The memory array of claim 13 , wherein one of the subset of the plurality of bit cells comprises a first input/output port coupled to a first bit line of the memory array, and a second output coupled to a second of the subset of the plurality of bit cells.