Layout of memory cells and input/output circuitry in a semiconductor memory device
View Patent ↗A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.
1. A semiconductor memory device comprising:
a memory cell array that is divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, and each of the subarrays having a sense amplifier unit;
a first pad column that is formed outside the memory cell array, the first pad column comprising a plurality of first pads that are arranged in a first direction being elongated to run substantially parallel to a word line;
a second pad column that is formed in a middle section of the memory cell array, the second pad column comprising a plurality of second pads that are arranged to be substantially parallel to the first direction,
a circuit that is arranged in the middle section or at the outside of the memory cell array; and
a line that is formed in a second direction substantially perpendicular to the first direction, the line being directly connected to the circuit,
wherein the sense amplifier unit includes a plurality of sense amplifier circuits which are arranged continuously in the first direction.
2. The semiconductor memory device according to claim 1 , wherein
the first pads are address pads,
the second pads are I/O pads,
the circuit comprises an address input circuit arranged in the middle section, and
the line directly connects the address pad and the address input circuit.
3. The semiconductor memory device according to claim 1 , further comprising a memory cell data reading sense amplifier circuit that is arranged in the memory cell array, wherein
the circuit comprises an I/O circuit arranged in the middle section, and
the line directly connects the data reading sense amplifier circuit and the I/O circuit.
4. The semiconductor memory device according to claim 2 , further comprising a memory cell data reading sense amplifier circuit that is arranged in the memory cell array; and
a second line that is formed in a direction substantially perpendicular to the subarray columns on the memory cell array,
wherein the circuit comprises an I/O circuit arranged in the middle section, and
the second line directly connects the data reading sense amplifier circuit and the I/O circuit.
5. The semiconductor memory device according to claim 1 , wherein
the first pads are I/O pads, and
the second pads are address pads.
6. The semiconductor memory device according to claim 1 , further comprising a memory cell data reading sense amplifier that is arranged in the memory cell array, wherein
the circuit comprises an I/O circuit arranged in the outside, and
the line directly connects the data reading sense amplifier circuit and the I/O circuit.
7. The semiconductor memory device according to claim 5 , further comprising a memory cell data reading sense amplifier circuit that is arranged in the memory cell array, wherein
the circuit comprises an I/O circuit arranged in the outside, and
the line directly connects the memory cell data reading sense amplifier circuit and the I/O circuit.
8. The semiconductor memory device according to claim 1 , further comprising an address register and a control logic circuit arranged in the middle section of the memory cell array and connected to the address input circuit.
9. The semiconductor memory device according to claim 1 , wherein the second pads are arranged in at least two lines in the middle section of the memory cell array.
10. The semiconductor memory device according to claim 1 , wherein the first pads are arranged along two opposite sides of the memory cell array.
11. The semiconductor memory device according to claim 1 , wherein each of the plurality of first pads and the plurality of second pads is arranged to be substantially parallel to a word line.
12. The semiconductor memory device according to claim 1 , wherein said sense amplifier unit has a length and a width such that the length is greater than the width, and said sense amplifier unit is arranged such that the length of said sense amplifier unit is oriented in the first direction.