High resolution overlapping bit segmented DAC
A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.
1. An overlapping segmented M-bit digital to analog converter (DAC) for receiving an M-bit binary input M IN and generating a corresponding DAC current, comprising:
a controller to receive M IN and generate in response, an S-bit upper range segment binary input S IN and an R-bit lower range segment binary input R IN , where R+S is greater than M, with the most significant bit of S IN having a binary weight of 2 M−1 , and the binary weight of 2 R being at least twice the binary weight of the least significant bit (LSB) of S IN
an S-bit high range DAC configured to receive S IN and generate, in response, a high range DAC current proportional, by a constant K, to the summed binary weight of the S IN bits;
an R-bit low range DAC configured to receive R IN and generate, in response, a low range DAC current proportional, by the constant K, to the summed binary weight of the R IN bits, and
a current summer to add the high-range DAC current and the low range DAC current to generate said current.
2. The overlapping segmented M-bit digital to analog converter (DAC) of claim 1 , wherein said controller is configured to detect transition points within the values of M IN and, in response, to add to S IN a transition quantity equal to at least the weight of the LSB position of S IN , and subtract said transition quantity from R IN .
3. The overlapping segmented M-bit digital to analog converter (DAC) of claim 2 , wherein said controller is configured to detect transition points within the values of M IN and to add said transition quantity to S IN and subtract said transition quantity from R IN such that R IN remains within a given operating range.
4. The overlapping segmented M-bit digital to analog converter (DAC) of claim 1 , wherein said R-bit low range DAC generates a full scale low range current FL in response to a full scale R-bit input of all 1s, and wherein the current output of said S-bit high range DAC changes, in response to a change in S IN of two S IN LSBs, an amount equal to one half of FL.
5. An overlapping segmented M-bit digital to analog converter (DAC) comprising:
a decoder to receive a given M-bit data and to generate an S-bit upper segment data and an R-bit lower segment data;
an S-bit sub-DAC to convert the S-bit upper segment data into an S-current proportional to the binary value of the S-bit upper segment data;
an R-bit sub-DAC to convert the R-bit lower segment data into an R-current proportional to the binary value of the R-bit lower segment data; and
a current summer to receive and generate an output DAC current based on a sum of the R-current and the S-current,
wherein S+R is greater than M,
wherein the coder maintains the value of the R-bit lower segment binary signal within a given range not including an all 1s condition, and
wherein it generates the S-bit upper segment binary signal and the R-bit lower segment binary signal so that the sum of the S-bit upper segment binary signal and the R-bit lower segment binary signal is equal to the given M-bit binary signal.
6. A digital frequency lock loop, comprising:
a digitally controlled oscillator (DCO) configured to receive an M-bit digital control input and to generate, in response, an output signal having a frequency FDCO;
a feedback sensor configured to sample the output signal and to generate a feedback data indicative of the FDCO value; and
a feedback controller configured to receive a reference frequency data FREF, compare FREF to FDCO, generate an error data representing a difference between FREF and FDCO, and to generate the M-bit digital control input based on the error data,
wherein the DCO includes an overlapping segment M-bit digital-to-analog converter (DAC) to receive the M-bit digital control data and to generate, in response an analog control data, and includes an analog oscillator configured to generate an analog signal having a frequency ω based on the analog control signal, and the overlapping segment M-bit DAC comprises:
a decoder to receive the M-bit data and to generate an S-bit upper segment data and an R-bit lower segment data;
an S-bit sub-DAC to convert the S-bit upper segment data into an S-current proportional to the binary value of the S-bit upper segment data;
an R-bit sub-DAC to convert the R-bit lower segment data into an R-current proportional to the binary value of the R-bit lower segment data; and
a current summer to receive and generate an output DAC current based on a sum of the R-current and the S-current,
wherein S+R is greater than M,
wherein the coder maintains the value of the R-bit lower segment binary signal within a given range not including an all 1s condition, and
wherein the coder generates the R-bit lower segment binary signal and the S-bit upper segment binary signal so that the sum of the S-bit upper segment binary signal and the L-bit lower segment binary signal is equal to the given M-bit binary signal.
7. A method for controlling a frequency lock loop receiving a reference frequency data F REF to generate an output signal Sout to have a frequency F DCO locked to the reference frequency, comprising:
sampling Sout to generate a feedback data indicative of F DCO ;
generating an error data based on said feedback data and said F REF indicating a difference between F DCO and F REF ;
generating an M-bit digitally controlled oscillator (DCO) control data signal based on said error data;
converting said M-bit DCO control data to an analog DCO control signal;
generating an analog oscillating signal giving a frequency based, at least in part, on said analog DCO control signal; and
generating Sout based on said analog oscillating signal,
wherein converting said M-bit DCO control data to an analog DCO control signal comprises:
generating an operating point data having an S-bit upper range operating point and an R-bit lower range operating point, where S+R is greater than M,
converting the S-bit upper range operating point to an upper range operating current
converting the R-bit lower range operating point to a lower range operating current, and
generating the analog DCO control signal based on a sum of the upper range operating current and the lower range operating current,
wherein the lower range operating current corresponding to a full-scale value of the R-bit lower range operating point is at least twice the upper range operating current corresponding to an S-bit upper range operating point of one least significant bit (LSB), and
wherein said generating an operating point data generates the S-bit upper range operating point and the R-bit lower range operating point to maintain the R-bit operating point within a given operating range within the full span of R-bit values.