Voltage reference circuit
View Patent ↗A bandgap voltage reference unit on an integrated circuit ( 101 ) includes a proportional-to-absolute-temperature (PTAT) current source ( 100 ) coupled to a bandgap voltage reference circuit ( 200 ) that includes a plurality of self-cascode MOSFET structures ( 201 - 204 ) that are cascaded together to form a PTAT voltage generator ( 205 ). The bandgap voltage reference circuit also includes a complementary-to-absolute-temperature (CTAT) device ( 260 ). A PTAT voltage from the PTAT voltage generator is added to a CTAT voltage from the CTAT device to produce an output voltage of the bandgap voltage reference unit, such that the output voltage is the bandgap voltage of the integrated circuit and such that the output voltage does not change with temperature.
1. A voltage reference circuit, comprising:
a proportional-to-absolute-temperature (PTAT) voltage generator that generates a PTAT voltage, the PTAT voltage generator including a cascade of a plurality of self-cascode MOSFET structures (SCMs), wherein each SCM includes a first transistor coupled to a second transistor in a diode configuration;
a complementary-to-absolute-temperature (CTAT) device, coupled to the PTAT voltage generator, the CTAT device having a CTAT voltage associated therewith;
means for adding the PTAT voltage and the CTAT voltage; and
an output, coupled to the means for adding, for providing a voltage reference that does not change with temperature.
2. The voltage reference circuit of claim 1 , wherein the first transistor operates in a linear region and the second transistor operates in a saturated region, and wherein the first transistor and the second transistor are biased in moderate inversion.
3. The voltage reference circuit of claim 1 , including a PTAT current source wherein each SCM is coupled to the current source.
4. The voltage reference circuit of claim 3 , wherein the PTAT current source includes a first transistor and a plurality of output transistors, wherein each output transistor has a mirror ratio with the first transistor of the PTAT current source, and wherein each output transistor operates in strong inversion and in a saturation region.
5. The voltage reference circuit of claim 4 , wherein a drain terminal of the second transistor of each SCM is coupled to a drain terminal of one of the output transistors of the current source.
6. The voltage reference circuit of claim 4 , wherein the PTAT current source includes a PMOS first transistor and a plurality of PMOS output transistors, each having a mirror ratio with the PMOS first transistor, that mirror a current through the PMOS first transistor, wherein each PMOS output transistor provides a PTAT current to each SCM, respectively.
7. The voltage reference circuit of claim 6 , wherein each of SCM includes a NMOS first transistor coupled to a NMOS second transistor in a diode configuration.
8. The voltage reference circuit of claim 7 , wherein the NMOS first transistor operates in a linear region and the NMOS second transistor operates in a saturated region, and wherein the NMOS first transistor and the NMOS second transistor are biased in moderate inversion.
9. The voltage reference circuit of claim 7 , wherein a drain terminal of a NMOS first transistor of a first SCM of the plurality of SCMs is coupled to the CTAT device, and a drain terminal of a NMOS second transistor of the first SCM of the plurality of SCMs is coupled to a drain terminal of a respective one of the PMOS output transistors of the PTAT current source.
10. The voltage reference circuit of claim 9 wherein a drain terminal of a NMOS first transistor of a second SCM of the plurality of SCMs is coupled to a source terminal of the NMOS first transistor of the first SCM of the plurality of SCMs, and a drain terminal of a NMOS second transistor of the second SCM of the plurality of SCMs is coupled to a drain terminal of a respective one of the PMOS output transistors of the PTAT current source.
11. The voltage reference circuit of claim 1 , wherein the CTAT device is a PNP bipolar junction transistor having a base terminal coupled to the PTAT voltage generator, an emitter terminal coupled to the output of the voltage reference circuit and a collector terminal coupled to ground potential, wherein the CTAT voltage is an emitter-to-base voltage of the PNP bipolar junction transistor.
12. The voltage reference circuit of claim 1 , wherein the CTAT device is a diode having one terminal coupled to the output of the voltage reference circuit and another terminal coupled to the PTAT voltage generator.
13. The voltage reference circuit of claim 4 , including a trim controller coupled to output transistors of the PTAT current source, wherein the trim controller selectively couples one or more of said output transistors to the PTAT voltage generator, to control amount of the PTAT voltage generated by the PTAT voltage generator.
14. A voltage regulator, comprising:
a voltage reference unit, the voltage reference unit including:
a proportional-to-absolute-temperature (PTAT) current source; and
a voltage reference circuit, coupled to the PTAT current source, the voltage reference circuit including:
a PTAT voltage generator that generates a PTAT voltage, the PTAT voltage generator including a cascade of a plurality of self-cascode MOSFET structures (SCM), wherein each SCM includes a NMOS first transistor and a NMOS second transistor coupled in a diode configuration;
a complementary-to-absolute-temperature (CTAT) device, coupled to the PTAT voltage generator, the CTAT device having a CTAT voltage associated therewith;
means for adding the PTAT voltage and the CTAT voltage; and
an output, coupled to the means for adding, for providing a voltage reference, wherein the voltage reference does not change with temperature.
15. The voltage regulator of claim 14 , wherein a drain terminal of the NMOS first transistor of a first SCM is coupled to the CTAT device, and a drain terminal of the NMOS second transistor of the first SCM is coupled to the PTAT current source.
16. The voltage regulator of claim 15 wherein a drain terminal of a NMOS first transistor of a second SCM is coupled to a source terminal of the NMOS first transistor of the first SCM, and a drain terminal of the NMOS second transistor of the first SCM is coupled to the PTAT current source, and a drain terminal of the NMOS second transistor of the second SCM is coupled to the PTAT current source.
17. The voltage regulator of claim 15 , wherein the CTAT device is a PNP bipolar junction transistor having a base terminal coupled to the drain terminal of the NMOS first transistor of the first SCM, an emitter terminal coupled to the output of the voltage reference circuit and a collector terminal coupled to ground potential, and wherein the CTAT voltage is an emitter-to-base voltage of the PNP bipolar junction transistor.
18. The voltage regulator of claim 16 , including a substrate having a bandgap voltage, wherein the PTAT voltage is selected such that the voltage reference is at the bandgap voltage.
19. An integrated circuit, comprising:
a substrate having a bandgap voltage; and
a bandgap voltage reference circuit, the bandgap voltage reference circuit including:
a proportional-to-absolute-temperature (PTAT) voltage generator that generates a PTAT voltage, the PTAT voltage generator including a cascade of a plurality of self-cascode MOSFET structures, wherein each SCM includes a first transistor coupled to a second transistor in a diode configuration;
a complementary-to-absolute-temperature (CTAT) device, coupled to the PTAT voltage generator, the CTAT device having a CTAT voltage associated therewith;
means for adding the PTAT voltage and the CTAT voltage; and
an output, coupled to the means for adding, for providing a voltage reference at a bandgap voltage, wherein the voltage reference does not change with temperature.
20. The integrated circuit of claim 19 , including a PTAT current source for providing a PTAT current to the bandgap voltage reference circuit.