MOS-gated power devices, methods, and integrated circuits
View Patent ↗MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
1. A semiconductor device, comprising:
an insulated trench in a semiconductor material, having a sidewall;
a gate electrode;
a semiconductor body region positioned so that voltage bias applied to the gate electrode can induce inversion in said body region to thereby create a channel;
permanent electrostatic charge positioned in proximity to said sidewall of said trench, in sufficient density to invert said semiconductor material at said sidewall; and
an insulated conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.
2. The device of claim 1 , wherein said permanent electrostatic charge comprises embedded cesium ions.
3. The device of claim 1 , wherein said insulated trench, below said shield, is substantially filled with dielectric.
4. The device of claim 1 , wherein said shield is taller in height than said gate electrode.
5. The device of claim 1 , wherein said shield is wider than said trench.
6. The device of claim 1 , further comprising a lightly doped region, of opposite conductivity type to said body, which is interposed between said trench and the location of said channel.
7. The device of claim 1 , built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.
8. A semiconductor device, comprising:
a first-conductivity-type source region;
a gate electrode, and a second-conductivity-type semiconductor body region positioned so that voltage bias applied to the gate electrode can invert said body region to thereby create a channel which receives majority carriers from said source region;
a trench which is substantially filled with dielectric material;
permanent electrostatic charge positioned in proximity to said sidewall of said trench, in sufficient density to invert said semiconductor material at said sidewall and thereby create an inverted region along said sidewall which can receive majority carriers which have passed through said channel region;
a first-conductivity-type drain region which is positioned to receive majority carriers which have passed through said inverted region; and
an insulated conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.
9. The device of claim 8 , wherein said permanent electrostatic charge comprises embedded cesium ions.
10. The device of claim 8 , wherein said insulated trench, below said shield, is substantially filled with dielectric.
11. The device of claim 8 , wherein said shield is taller in height than said gate electrode.
12. The device of claim 8 , further comprising a lightly doped region, of said first conductivity type, which is electrically interposed between said trench and the location of said channel.
13. The device of claim 8 , wherein said shield lies entirely within said trench.
14. The device of claim 8 , wherein said shield is wider than said trench.
15. A semiconductor device, comprising, in a semiconductor mass:
a lateral transistor, comprising a first-conductivity-type source region, and a gate electrode positioned to control lateral flow of majority carriers out of said source region;
a trench, which extends down into a second-conductivity-type drift region, which is substantially filled with dielectric material, and which has permanent electrostatic charge positioned at sidewalls thereof, in sufficient density to invert said second-conductivity-type drift region at said sidewall and thereby create an inverted region along said sidewall which can receive majority carriers which have passed through said channel region;
a first-conductivity-type drain region which is positioned to receive majority carriers which have passed through said inverted region; and
an insulated conductive shield layer which is positioned above the dielectric material in said insulated trench, and not electrically connected to said gate;
whereby capacitive coupling from said gate to said drain region is reduced.
16. The device of claim 15 , wherein said permanent electrostatic charge comprises embedded cesium ions.
17. The device of claim 15 , wherein said shield is taller in height than said gate electrode.
18. The device of claim 15 , wherein said shield lies entirely within said trench.
19. The device of claim 15 , wherein said shield is wider than said trench.
20. The device of claim 15 , further comprising a lightly doped region, of said first conductivity type to said body, which is interposed between said trench and the location of said channel.
21. The device of claim 1 , further comprising a source metallization contacting said source region and at least partially overlying said shield.
22. The device of claim 8 , further comprising a source metallization contacting said source region and at least partially overlying said shield.
23. The device of claim 15 , further comprising a source metallization contacting said source region and at least partially overlying said shield.