Semiconductor device and fabricating method thereof

1. A method of fabricating a semiconductor device, comprising:

forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area;

partially etching the polysilicon layer in the low-voltage area;

forming an anti-reflective layer on the partially etched polysilicon layer to reduce a step difference between the high-voltage and low-voltage areas;

forming a first photoresist pattern in the high-voltage and low-voltage areas, respectively; and

forming a high-voltage gate and a low-voltage gate by etching the partially etched polysilicon layer using the first photoresist pattern as an etch mask.

2. The method of claim 1 , wherein the polysilicon layer in the low-voltage area has a smaller thickness than the polysilicon layer in the high-voltage area.

3. The method of claim 2 , wherein partially etching the polysilicon layer in the low-voltage area comprises dry etching for a predetermined or target time.

4. The method of claim 1 , wherein forming the anti-reflective layer comprises coating an anti-reflective material on the polysilicon layer in the high-voltage and low-voltage areas.

5. The method of claim 4 , further comprising heating the anti-reflective material using an oven or a hot plate at a temperature of about 100-400° C.

6. The method of claim 1 , further comprising forming a device isolation layer by shallow trench isolation between the high-voltage area and the low-voltage area.

7. The method of claim 1 , further comprising forming an n-well in each of the high-voltage and low-voltage areas by ion implantation of N-type impurities.

8. The method of claim 1 , wherein forming the polysilicon layer comprises chemical vapor deposition using a plasma into which a silicon source gas is introduced.

9. The method of claim 1 , further comprising, prior to partially etching the polysilicon layer in the low-voltage area, forming a second photoresist pattern in the high-voltage area, exposing a surface of the low-voltage area.

10. The method of claim 1 , wherein the polysilicon layer comprises a first portion in the high-voltage area and a second portion in the low-voltage area, the first portion being thicker than the second portion.

11. The method of claim 10 , wherein the first and second portions have a thickness corresponding to operating voltages for the high-voltage and low-voltage devices.

12. The method of claim 10 , wherein the step difference of the portions of the polysilicon layer between the high-voltage and low-voltage are reduced and/or eliminated by the anti-reflective layer.

13. The method of claim 1 , further comprising forming a gate oxide layer on the semiconductor substrate by a wet oxidation process conducted at a temperature of about 800-1000° C.

14. The method of claim 13 , wherein said gate oxide layer generally has a thickness in the high voltage region 20 to 100 percent greater than in the low voltage region.

15. The method of claim 1 , wherein the anti-reflective layer comprises an inorganic anti-reflective layer.

16. The method of claim 15 , wherein the inorganic anti-reflective layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

17. The method of claim 1 , wherein the anti-reflective layer comprises an organic anti-reflective layer.

18. The method of claim 17 , wherein the organic anti-reflective layer comprises a hydrocarbon-based polymer with a carboxylate or sulfonyl group.

19. The method of claim 1 , further comprising forming an p-well in each of the high-voltage and low-voltage areas by ion implantation of P-type impurities.

20. The method of claim 1 , wherein partially etching the polysilicon layer comprises dry etching the polysilicon layer for a predetermined or target time, using an empirically determined etch rate to determine the predetermined or target time.