One time programmable memory device and manufacturing method of one time programmable memory device
View Patent ↗Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays.
1. A method comprising:
forming a common source in a linear configuration on a semiconductor substrate;
forming a gate dielectric layer on the semiconductor substrate at both sides of the source;
forming a gate over the gate dielectric layer;
forming a spacer between the gates and at both side walls of the gate; and
forming a drain on the semiconductor substrate at both sides of the spacer, wherein the source is formed having a memory common source structure and the common source, the gate, and the drain form a one time programmable memory device.
2. The method of claim 1 , wherein the source is formed having a self aligned source structure.
3. The method of claim 2 , wherein the source is at least partially formed using a shallow trench isolation process of a logic process.
4. The method of claim 1 , wherein the source is through an ion implantation process of a logic process.
5. The method of claim 1 , including:
forming an insulation layer over the semiconductor substrate including the drain, the spacer, and the gate.
6. The method of claim 5 , including:
forming a contact plug connected to the drain and a metal wiring connected to the contact plug over the insulation layer.
7. The method of claim 1 , wherein the one time programmable memory device has a cell array structure where the gate functions as a word line and the metal wiring functions as a bit line.
8. An apparatus comprising:
a common source formed in a linear configuration on a semiconductor substrate;
a gate dielectric layer formed over the semiconductor substrate at both sides of the source;
a gate formed over the gate dielectric layer;
a spacer formed between the gates and at both side walls of the gate; and
a drain on the semiconductor substrate at both sides of the spacer, wherein the common source, gate, and drain form a one time programmable memory device.
9. The apparatus of claim 8 , wherein the source has a self aligned source structure.
10. The apparatus of claim 8 , wherein the source is formed having a memory common source structure.
11. The apparatus of claim 8 , including:
an insulation layer formed over the semiconductor substrate including the drain, the spacer, and the gate.
12. The apparatus of claim 11 , including:
a contact plug formed over the insulation layer and connected to the drain; and
a metal wiring formed over the insulation layer and connected to the contact plug.
13. The apparatus of claim 8 , wherein the one time programmable memory device has a cell array structure where the gate functions as a word line and the metal wiring functions as a bit line.
14. The apparatus of claim 13 , wherein the one time programmable memory device has a program mode where Vcc is applied to the gate and drain of a cell to be programmed, and GND is maintained in the gate and in the drain of other cells.
15. The apparatus of claim 14 , wherein GND is maintained in the sources of all cells.
16. The apparatus of claim 8 , wherein the one time programmable memory device has a read mode where Vcc is applied to the gate and drain of a cell to be read, a negative potential voltage is applied to the gates of other cells, and the drains of other cells are floated.
17. The apparatus of claim 16 , wherein voltage of 0.5 V to 2 V is applied to the sources of all cells.