Non-volatile semiconductor memory, and the method thereof
View Patent ↗A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs 1 and Qs 2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10 . The control circuit 11 records two values for at least a plurality of first memory cell transistors Q 0 , Q 1 , Q 32 and Q 33 respectively adjacent to the selection transistors Qs 1 and Qs 2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q 2 ˜Q 31 other than the first memory cell transistors.
1. A non-volatile semiconductor memory device, comprising:
a non-volatile memory cell array for recording multiple values by setting a plurality of different threshold voltages to each memory cell transistor, wherein each memory cell transistor is connected in series between selection transistors on two terminals of a selected bit line; and
a control circuit for controlling programmed data of the memory cell array,
wherein the control circuit records two values for at least a plurality of first memory cell transistors respectively adjacent to the selection transistors on the two terminals, and records more than three multiple values for a plurality of second transistors other than the first memory cell transistors, and sets a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and the verifying voltage for recording the data has a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.
2. The non-volatile semiconductor memory device as claimed in claim 1 , wherein the control circuit records the two values for two of the first memory cell transistors respectively adjacent to the selection transistors on the two terminals.
3. The non-volatile semiconductor memory device as claimed in claim 2 , wherein the control circuit divides the data into a predetermined number and writes the data into each page of the first memory cell transistors recorded by the two values for recording the data.
4. The non-volatile semiconductor memory device as claimed in claim 1 , wherein the verifying voltage for recording the data has a low threshold voltage level which is lower than the maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.
5. A write-in method for a non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device comprises a non-volatile memory cell array and a control circuit, the memory cell array records multiple values by setting a plurality of different threshold voltages to each memory cell transistor, each memory cell transistor is coupled in series between selection transistors on two terminals of a selected bit line, and the control circuit controls programmed data of the memory cell array, comprising:
a control step for recording two values for at least a plurality of first memory cell transistors respectively adjacent to the selection transistors on the two terminals, and recording more than three multiple values for a plurality of second transistors other than the first memory cell transistors; and
setting a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and the verifying voltage for recording the data has a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.
6. The write-in method as claimed in claim 5 , wherein the control step further comprises the step of:
recording the two values for two of the first memory cell transistors respectively adjacent to the selection transistors on the two terminals.
7. The write-in method as claimed in claim 5 , wherein the control step further comprises the step of:
dividing the data into a predetermined number and writing the data into each page of the first memory cell transistors recorded by the two values for recording the data.
8. The write-in method as claimed in claim 5 , wherein the verifying voltage for recording the data has a low threshold voltage level which is lower than the maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.