Ferroelectric tunnel FET switch and memory
View Patent ↗A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.
1. A ferroelectric tunnel FET comprising a ferroelectric gate stack and a band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, such that the combined effect of band-to-band tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions than for any reported tunnel FET or any reported ferroelectric FET.
2. A ferroelectric tunnel FET as defined in claim 1 , comprising at least a gate of metal or polysilicon, a ferroelectric material, a highly n-type doped silicon, a low doped or intrinsic silicon and a highly p-type doped silicon.
3. A ferroelectric tunnel FET as defined in claim 2 , comprising a dielectric capping on the ferroelectric material.
4. A ferroelectric tunnel FET as defined in claim 2 , comprising a thin interfacial dielectric between the ferroelectric material and the low-doped or intrinsic silicon.
5. A ferroelectric tunnel FET as defined in claim 4 , wherein the thin interfacial dielectric is made of silicon dioxide.
6. A ferroelectric Tunnel FET one transistor (1T) memory based on the hysteretic behavior generated by ferroelectric material, the ultra-low Ioff offered by the reversed biased silicon p-i-n junction and the abrupt off-on and on-off transitions.
7. A ferroelectric tunnel FET as defined in claim 1 using other materials than ferroelectrics in said gate stack able to provide a positive feedback in the gate stack or negative gate capacitance for tunnel FET based on gated pin junction.
8. A ferroelectric tunnel FET as defined in claim 7 , wherein said other materials are materials offering polaronic effects or bias dependent dielectric permittivity.
9. A tunneling device as defined in claim 1 wherein the ferroelectric gate stack is on other than silicon semiconductor materials or heterostructures for the implementation of the tunneling junction.
10. A Double-gate, or multi-gate, or FIN-FET, or Silicon-On-insulator MOSFET or wrapped-gate nanowire technological implementations using the ferroelectric tunnel FET defined in claim 1 .
11. A unipolar or ambipolar ferroelectric carbon nanotube tunnel FET comprising a carbon nanotube tunneling device with ferroelectric gate stack and band-to-band tunneling mechanism.
12. A semiconductor device based on a gated junction that combines very steep switching the band-to-band tunneling and the positive feedback or negative capacitance associated with a ferroelectric gate stack, wherein very steep switching means showing a slope lower than 60 mV/decade at room temperature.