Field effect transistor
View Patent ↗A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer; and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.
1. A field effect transistor comprising:
a Schottky layer;
a stopper layer formed of InGaP and provided in a recess region on said Schottky layer;
a cap layer provided on said stopper layer and formed of GaAs; and
a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between said stopper layer and said cap layer,
wherein said cap layer comprises:
a high concentration cap layer; and
a low concentration cap layer having an impurity provided directly or indirectly under said high concentration cap layer and having an impurity concentration lower than said high concentration cap layer,
wherein said barrier rising suppression region is provided for a layer between said stopper layer and said low concentration cap layer, and comprises a GaAs electron compensation layer which contains said impurity of a higher concentration than said low concentration cap layer.
2. The field effect transistor according to claim 1 , wherein said stopper layer formed from order-InGaP which forms a spontaneous superlattice.
3. The field effect transistor according to claim 2 , wherein said stopper layer is formed without intentionally adding any impurity.
4. The field effect transistor according to claim 1 , wherein said low concentration cap layer has a film thickness in a range from 50 nm to 100 nm.
5. The field effect transistor according to claim 1 , wherein said Schottky layer is formed without intentionally adding an n-type impurity.
6. The field effect transistor according to claim 1 , wherein said Schottky layer is mainly formed of AlGaAs.
7. The field effect transistor according to claim 1 , wherein said recess region is formed such that an opening in said cap layer is coincident with an opening in said stopper layer.
8. The field effect transistor according to claim 1 , wherein said recess region is formed such that an opening in said cap layer is wider than an opening in said stopper layer.
9. The field effect transistor according to claim 8 , wherein said opening in said cap layer is formed such that an opening in said high concentration cap layer is wider than an opening in said low concentration cap layer.
10. The field effect transistor according to claim 1 , wherein said impurity is Si.
11. A field effect transistor comprising:
a Schottky layer;
a stopper layer ( 9 ) formed of InGaP and provided in a recess region ( 20 ) on said Schottky layer;
a cap layer ( 11 , 12 ) provided on said stopper layer and formed of GaAs; and
a barrier rising suppression region ( 10 ) comprised of a Si-doped GaAs carrier compensation layer provided in the recess region ( 20 ) on said Schottky layer, the Si-doped GaAs carrier compensation layer located between said stopper layer ( 9 ) and said cap layer ( 11 , 12 ), the barrier rising suppression region ( 10 ) configured to suppress rising of a potential barrier due to interface charge between said stopper layer and said cap layer,
wherein said cap layer comprises:
a high concentration cap layer ( 12 ); and
a low concentration cap layer ( 11 ) provided directly or indirectly under said high concentration cap layer and having an impurity concentration lower than said high concentration cap layer and lower than said Si-doped GaAs carrier compensation layer.
12. The field effect transistor according to claim 11 , wherein said Si-doped GaAs carrier compensation layer has a Si impurity of approximately 3.0×10 18 cm −3 .